Nxp Semiconductors OM11043 Data Sheet

LPC1769_68_67_66_65_64_63

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Eight DMA channels. Each channel can support an unidirectional transfer.

16 DMA request lines.

Single DMA and burst DMA request signals. Each peripheral connected to the DMA 
Controller can assert either a burst DMA request or a single DMA request. The DMA 
burst size is set by programming the DMA Controller.

Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and 
peripheral-to-peripheral transfers are supported.

Scatter or gather DMA is supported through the use of linked lists. This means that 
the source and destination areas do not have to occupy contiguous areas of memory.

Hardware DMA channel priority.

AHB slave DMA programming interface. The DMA Controller is programmed by 
writing to the DMA control registers over the AHB slave interface.

One AHB bus master for transferring data. The interface transfers data when a DMA 
request goes active. 

32-bit AHB master bus width.

Incrementing or non-incrementing addressing for source and destination.

Programmable DMA burst size. The DMA burst size can be programmed to more 
efficiently transfer data.

Internal four-word FIFO per channel.

Supports 8, 16, and 32-bit wide transactions.

Big-endian and little-endian support. The DMA Controller defaults to little-endian 
mode on reset.

An interrupt to the processor can be generated on a DMA completion or when a DMA 
error has occurred.

Raw interrupt status. The DMA error and DMA count raw interrupt status can be read 
prior to masking.

Device pins that are not connected to a specific peripheral function are controlled by the 
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate 
registers allow setting or clearing any number of outputs simultaneously. The value of the 
output register may be read back as well as the current state of the port pins.

LPC17xx use accelerated GPIO functions:

GPIO registers are accessed through the AHB multilayer bus so that the fastest 
possible I/O timing can be achieved.

Mask registers allow treating sets of port bits as a group, leaving other bits 
unchanged.

All GPIO registers are byte and half-word addressable.

Entire port value can be written in one instruction.

Support for Cortex-M3 bit banding.

Support for use with the GPDMA controller.