Nxp Semiconductors OM11043 Data Sheet

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

The LPC17xx provide two independent power domains that allow the bulk of the device to 
have power removed while maintaining operation of the RTC and the backup Registers.

On the LPC17xx, I/O pads are powered by the 3.3 V (V

DD(3V3)

) pins, while the 

V

DD(REG)(3V3)

 pin powers the on-chip voltage regulator which in turn provides power to the 

CPU and most of the peripherals.

Depending on the LPC17xx application, a design can use two power options to manage 
power consumption.

The first option assumes that power consumption is not a concern and the design ties the 
V

DD(3V3)

 and V

DD(REG)(3V3)

 pins together. This approach requires only one 3.3 V power 

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not 
support powering down the I/O pad ring “on the fly” while keeping the CPU and 
peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V

DD(3V3)

) and 

a dedicated 3.3 V supply for the CPU (V

DD(REG)(3V3)

). Having the on-chip voltage regulator 

powered independently from the I/O pad ring enables shutting down of the I/O pad power 
supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of 
power to operate, which can be supplied by an external battery. The device core power 
(V

DD(REG)(3V3)

) is used to operate the RTC whenever V

DD(REG)(3V3)

 is present. Therefore, 

there is no power drain from the RTC battery when V

DD(REG)(3V3)

 is available.