Nxp Semiconductors OM11043 Data Sheet

LPC1769_68_67_66_65_64_63

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2014. All rights reserved.

 







V

DD(3V3)

supply voltage (3.3 V)

external rail

2.4

3.3

3.6

V

V

DD(REG)(3V3)

regulator supply voltage 
(3.3 V)

2.4

3.3

3.6

V

V

DDA

analog 3.3 V pad supply 
voltage

2.5

3.3

3.6

V

V

i(VBAT)

input voltage on pin 
VBAT

2.1

3.3

3.6

V

V

i(VREFP)

input voltage on pin 
VREFP

2.5

3.3

V

DDA

V

I

DD(REG)(3V3)

regulator supply current 
(3.3 V)

active mode; code

while(1){}

executed from flash; all 
peripherals disabled; 
PCLK = 

CCLK

⁄

8

CCLK = 12 MHz; PLL 
disabled

-

7

-

mA

CCLK = 100 MHz; PLL 
enabled

-

42

-

mA

CCLK = 100 MHz; PLL 
enabled (LPC1769)

-

50

-

mA

CCLK = 120 MHz; PLL 
enabled (LPC1769)

-

67

-

mA

sleep mode

-

2

-

mA

deep sleep mode

-

240

-

A

power-down mode

-

31

-

A

deep power-down mode; 
RTC running

-

630

-

nA

I

BAT

battery supply current

deep power-down mode; 
RTC running

V

DD(REG)(3V3)

 present

-

530

-

nA

V

DD(REG)(3V3)

 not 

present

-

1.1

-

A

I

DD(IO)

I/O supply current

deep sleep mode

-

40

-

nA

power-down mode

-

40

-

nA

deep power-down mode

-

10

-

nA