Nxp Semiconductors OM11043 Data Sheet
LPC1769_68_67_66_65_64_63
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Product data sheet
Rev. 9.5 — 24 June 2014
61 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
12.7 SSP interface
The maximum SSP speed is 33 Mbit/s in master mode or 8 Mbit/s in slave mode. In slave
mode, the maximum SSP clock rate must be 1/12 of the SSP PCLK clock rate.
mode, the maximum SSP clock rate must be 1/12 of the SSP PCLK clock rate.
Table 16.
Dynamic characteristics: SSP pins in SPI mode
C
L
= 30 pF for all SSP pins; T
amb
=
40
C to 85
C; V
DD(3V3)
= 3.3 V to 3.6 V; input slew = 1 ns;
sampled at 10 % and 90 % of the signal level. Values guaranteed by design.
Symbol
Parameter
Conditions
Min
Max
Unit
SSP master
t
DS
data set-up time
in SPI mode
16.1
-
ns
t
DH
data hold time
in SPI mode
0
-
ns
t
v(Q)
data output valid time
in SPI mode
-
2.5
ns
t
h(Q)
data output hold time
in SPI mode
0
-
ns
SSP slave
t
DS
data set-up time
in SPI mode
16.1
-
ns
t
DH
data hold time
in SPI mode
0
-
ns
t
v(Q)
data output valid time
in SPI mode
-
2.5
ns
t
h(Q)
data output hold time
in SPI mode
0
-
ns
Fig 21. SSP master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID
DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
DATA VALID
DATA VALID
t
h(Q)
DATA VALID
DATA VALID
t
v(Q)
CPHA = 1
CPHA = 0
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