STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 EVAL6460 Data Sheet

   

   

   

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 Doc ID 17713 Rev 1

The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can 
periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register.

This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the 
WDEnable bit in the WatchDogCfg register.

When the Watchdog timeout event happens, L6460 sets to ‘1’ a latched bit WDTimeOut in 
theWatchDogStatus register that can be read using SPI interface; once this bit is set it can 
be cleared in three ways:

–

by writing a ‘1’ in the WDClear bit in the WatchDogStatus register.

–

by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register.

–

by a POR event.

The Watchdog function includes also a warning bit WDWarning to indicate, via serial 
interface or via the circuit called Interrupt Controller (see 

) that the watchdog is 

near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period 
(WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut 
signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit.

The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective 
programmed WD time is changed in the register only when the watchdog circuit is serviced 
by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of 
the WD delay value is loaded. 

The watchdog timer can be programmed to generate different timeouts using the 
WDdelay[3:0] bits in the WatchDogCfg register according to following table.

Frequency divider

 

Fosc 

WD_clk  Watchdog counter

 

WDd

e

lay

[3

:0

] 

WD

War

n

in

g 

WDT

im

e

Ou

t 

To SPI 

WD_

E

n

_

n

Rs

t 

WDE

n

ab

le 

W

D

_

req

_nR

s

t 

To nRSTint 

generation circuit

 

Clr

W

Do

g