STMicroelectronics 19 V - 75 W SMPS using the L6563 and the L6566A EVL6566A-75WES4 EVL6566A-75WES4 Data Sheet

Doc ID 16116 Rev 4

23/43

Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator 
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A 
pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a 
separate resistor divider (R3 high, R4 low, see 

). This divider is selected so that 

the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually 
larger than the maximum Vo that can be expected.

Example: V

O

 = 400 V, V

OX 

= 434 V. Select: R3 = 8.8 M

Ω; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 

51 k

Ω.

When this function is triggered, the gate drive activity is immediately stopped until the 
voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be 
selected without any constraints. The unique criterion is that both dividers have to sink a 
current from the output bus which needs to be significantly higher than the bias current of 
both INV and PFC_OK pins.

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