STMicroelectronics 19 V - 75 W SMPS using the L6563 and the L6566A EVL6566A-75WES4 User Manuals

Table of Contents

• Figure 1. Block diagram

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• 1 Description

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• 2 Maximum ratings

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  • 2.1 Absolute maximum ratings

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    • Table 1. Absolute maximum ratings

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  • 2.2 Thermal data

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    • Table 2. Thermal data

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• 3 Pin connection

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  • Figure 2. Pin connection

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  • Table 3. Pin description

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  • Figure 3. Typical system block diagram

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• 4 Electrical characteristics

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  • Table 4. Electrical characteristics

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• 5 Typical electrical performance

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  • Figure 4. IC consumption vs VCC

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  • Figure 5. IC consumption vs TJ

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  • Figure 6. Vcc Zener voltage vs TJ

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  • Figure 7. Start-up and UVLO vs TJ

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  • Figure 8. Feedback reference vs TJ

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  • Figure 9. E/A output clamp levels vs TJ

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  • Figure 10. UVLO saturation vs TJ

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  • Figure 11. OVP levels vs TJ

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  • Figure 12. Inductor saturation threshold vs TJ

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  • Figure 13. Vcs clamp vs TJ

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  • Figure 14. ZCD sink/source capability vs TJ

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  • Figure 15. ZCD clamp level vs TJ

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  • Figure 16. TBO clamp vs TJ

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  • Figure 17. VVFF - VTBO dropout vs TJ

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  • Figure 18. IINV - ITBO current mismatch vs TJ

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  • Figure 19. IINV - ITBO mismatch vs ITBO current

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  • Figure 20. R discharge vs TJ

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  • Figure 21. Line drop detection threshold vs TJ

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  • Figure 22. VMULTpk - VVFF dropout vs TJ

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  • Figure 23. PFC_OK threshold vs TJ

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  • Figure 24. PFC_OK FFD threshold vs TJ

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  • Figure 25. PWM_LATCH high saturation vs TJ

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  • Figure 26. RUN threshold vs TJ

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  • Figure 27. PWM_STOP low saturation vs TJ

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  • Figure 28. Multiplier characteristics @ VFF = 1 V

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  • Figure 29. Multiplier characteristics @ VFF = 3 V

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  • Figure 30. Multiplier gain vs TJ

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  • Figure 31. Gate drive clamp vs TJ

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  • Figure 32. Gate drive output saturation vs TJ

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  • Figure 33. Delay to output vs TJ

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  • Figure 34. Start-up timer period vs TJ

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• 6 Application information

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  • 6.1 Overvoltage protection

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    • Figure 35. Output voltage setting, OVP and FFP functions: internal block diagram

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  • 6.2 Feedback failure protection (FFP)

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  • 6.3 Voltage feedforward

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    • Figure 36. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic

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    • Figure 37. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current

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  • 6.4 THD optimizer circuit

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    • Figure 38. THD optimizer circuit

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    • Figure 39. THD optimization: standard TM PFC controller (left side) and L6563S (right side)

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  • 6.5 Tracking boost function

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    • Figure 40. Tracking boost block

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    • Figure 41. Tracking output voltage vs Input voltage characteristic with TBO

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  • 6.6 Inductor saturation detection

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    • Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method

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  • 6.7 Power management/housekeeping functions

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    • Figure 43. Interface circuits that let dc-dc converter's controller IC drive L6563S in burst mode

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    • Figure 44. Interface circuits that let the L6563S switch on or off a PWM controller

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    • Figure 45. Interface circuits for power up sequencing when dc-dc has the SS function

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    • Figure 46. Interface circuits for actual power-up sequencing (master PFC)

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    • Figure 47. Brownout protection (master PFC)

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    • Table 5. Summary of L6563S idle states

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• 7 Application examples and ideas

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  • Figure 48. Demonstration board EVL6563S-100W, wide-range mains: electrical schematic

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  • Figure 49. L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard

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  • Figure 50. L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard

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  • Figure 51. L6563S 100 W TM PFC demonstration board: input current waveform @230-50 Hz - 100 W load

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  • Figure 52. L6563S 100W TM PFC demonstration board: input current waveform @100 V-50 Hz - 100 W load

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  • Figure 53. EVL6563S-250W TM PFC demonstration board: electrical schematic

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  • Figure 54. EVL6563S-400W FOT PFC demonstration board: electrical schematic

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  • Figure 55. EVL6563S-ZRC200W 200W PFC pre-regulator with ripple-free input current: electrical schematic

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• 8 Package mechanical data

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  • Table 6. SO14 mechanical data

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  • Figure 56. Package dimensions

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• 9 Ordering codes

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  • Table 7. Ordering information

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• 10 Revision history

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  • Table 8. Document revision history

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