STMicroelectronics 19 V - 75 W SMPS using the L6563 and the L6566A EVL6566A-75WES4 EVL6566A-75WES4 Data Sheet
Product codes
EVL6566A-75WES4
Pin connection
L6563S
8/43
Doc ID 16116 Rev 4
3 Pin
connection
Figure 2.
Pin connection
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Table 3.
Pin description
n°
Name
Function
1
INV
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
regulator is fed into the pin through a resistor divider.
The pin normally features high impedance but, if the tracking boost function is used, an internal
current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to
change the output voltage so that it tracks the mains voltage.
current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to
change the output voltage so that it tracks the mains voltage.
2
COMP
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
below 2.4 V the gate driver output will be inhibited (burst-mode operation).
below 2.4 V the gate driver output will be inhibited (burst-mode operation).
3
MULT
Mains input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.
4
CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET’s turn-off.
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET’s turn-off.
A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
converter and limits the stress of the power components.
saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
converter and limits the stress of the power components.
5
VFF
Second input to the multiplier for 1/V
2
function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak
voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage.
Never connect the pin directly to GND but with a resistor ranging from 100 k
information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak
voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage.
Never connect the pin directly to GND but with a resistor ranging from 100 k
Ω (minimum)
to 2 M
Ω (maximum).
6
TBO
Tracking boost function. This pin provides a buffered VFF voltage. A resistor connected
between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the
output voltage is changed proportionally to the mains voltage (tracking boost). If this function is
not used leave this pin open.
between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the
output voltage is changed proportionally to the mains voltage (tracking boost). If this function is
not used leave this pin open.