IBM Intel Xeon E7430 44E4470 Data Sheet
Product codes
44E4470
Electrical Specifications
34
Intel® Xeon® Processor 7400 Series Datasheet
2.11.4
Platform Environmental Control Interface (PECI) DC
Specifications
PECI is an Intel proprietary one-wire bus interface that provides a communication
channel between Intel processor and external thermal monitoring devices. The Intel®
Xeon® Processor 7400 Series contains Digital Thermal Sensors (DTS) distributed
throughout the die. These sensors are implemented as analog-to-digital converters
calibrated at the factory for reasonable accuracy to provide a digital representation of
relative processor temperature. PECI provides an interface to relay the highest DTS
temperature within a die to external management devices for thermal/fan speed
control. More detailed information may be found in
channel between Intel processor and external thermal monitoring devices. The Intel®
Xeon® Processor 7400 Series contains Digital Thermal Sensors (DTS) distributed
throughout the die. These sensors are implemented as analog-to-digital converters
calibrated at the factory for reasonable accuracy to provide a digital representation of
relative processor temperature. PECI provides an interface to relay the highest DTS
temperature within a die to external management devices for thermal/fan speed
control. More detailed information may be found in
and the RS - Platform Environment Control Interface (PECI)
Specification.
2.11.4.1
DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to
Note:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
Table 2-16. PECI DC Electrical Limits
Symbol
Definition and
Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A
V
V
n
Negative-edge
threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold
voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output
source
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state
leakage to V
TT
(V
leak
= V
OL
)
N/A
50
µA
I
leak-
High impedance
leakage to GND
(V
leak
= V
OH
)
N/A
10
µA
C
bus
Bus capacitance
N/A
10
pF
V
noise
Signal noise immunity
above 300 MHz
0.1 * V
TT
N/A
V
p-p