IBM Intel Xeon E7430 44E4470 Data Sheet

Intel® Xeon® Processor 7400 Series Datasheet

35

The input buffers in both client and host models must use a Schmitt-triggered input 
design for improved noise immunity. Use 

 as a guide for input buffer design.

Routing topologies are dependent on the processors supported and the chipset used in 
the design. Please refer to the appropriate platform design guidelines for specific 
implementation details.

 

In most cases, termination resistors are not required as these 

are integrated into the processor silicon. See 

 for details on which signals do 

not include on-die termination. Please refer to 

 for R

TT

 values.

Valid high and low levels are determined by the input buffers via comparing with a 
reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, 
and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END are the reference 
voltage for the FSB 4X data signals, GTLREF_ADD_MID and GTLREF_ADD_END are the 
reference voltage for the FSB 2X address signals and common clock signals. 

lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and 
GTLREF_ADD_END specifications.

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard 
using high precision voltage divider circuits. Refer to the appropriate platform design 
guidelines for implementation details.

Minimum V

P

Maximum V

P

Minimum V

N

Maximum V

N

PECI High Range

PECI Low Range

Valid Input
Signal Range

Minimum
Hysteresis

V

TT

PECI Ground