Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
11
NOTE:
The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each
multiplier is only valid for use on the product of the frequency indicated in Table 1.
The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each
multiplier is only valid for use on the product of the frequency indicated in Table 1.
Clock multiplying within the processor is provided by the internal PLL, requiring a constant frequency BCLK input. The
BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes. The BCLK
frequency ratio can be changed when RESET# is active, assuming that all RESET# specifications are met.
BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes. The BCLK
frequency ratio can be changed when RESET# is active, assuming that all RESET# specifications are met.
See Figure 1 for the timing relationship between the system bus multiplier signals, RESET#, and normal processor
operation. Using CRESET# (CMOS Reset) and the timing shown in Figure 1, the circuit in Figure 2 can be used to share
these configuration signals. The component used as the multiplexer must not have outputs that drive higher than 2.5V in
order to meet the processor’s 2.5V tolerant buffer specifications.
operation. Using CRESET# (CMOS Reset) and the timing shown in Figure 1, the circuit in Figure 2 can be used to share
these configuration signals. The component used as the multiplexer must not have outputs that drive higher than 2.5V in
order to meet the processor’s 2.5V tolerant buffer specifications.
As shown in Figure 2, the pull-up resistors between the multiplexer and the processor (1K ohm) force a “safe” ratio into
the processor in the event that the processor powers up before the multiplexer and/or core logic. This prevents the
processor from ever seeing a ratio higher than the final ratio.
the processor in the event that the processor powers up before the multiplexer and/or core logic. This prevents the
processor from ever seeing a ratio higher than the final ratio.
If the multiplexer were powered by VCC2.5, a pull-down resistor could be used on CRESET# instead of the four pull-up
resistors between the multiplexer and the Pentium® III Xeon™ processor at 600 MHz+. In this case, the multiplexer must
be designed such that the compatibility inputs are truly ignored, as their state is unknown.
resistors between the multiplexer and the Pentium® III Xeon™ processor at 600 MHz+. In this case, the multiplexer must
be designed such that the compatibility inputs are truly ignored, as their state is unknown.
In any case, the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. This may
require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already
compatible.
require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already
compatible.
BCLK
RESET#
CRESET#
Ratio Pins#
Compatibility
≤
Final Ratio
Final Ratio
000917
Figure 1. Timing Diagram of Clock Ratio Signals