Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
13
recommended range of values to support for the processor core. A ‘1’ in this table refers to an open pin and ‘0’ refers to a
short to ground. The definition provided below is a superset of the definition previously defined for the Pentium Pro
processor (VID4 was not used by the Pentium Pro processor) and is common to the Pentium® III Xeon™ processor at
600 MHz+ (for VCC_CORE only). The power supply must supply the voltage that is requested or it must disable itself.
short to ground. The definition provided below is a superset of the definition previously defined for the Pentium Pro
processor (VID4 was not used by the Pentium Pro processor) and is common to the Pentium® III Xeon™ processor at
600 MHz+ (for VCC_CORE only). The power supply must supply the voltage that is requested or it must disable itself.
Table 2. Voltage Identification
1
VID4
VID3
VID2
VID1
VID0
VCC_CORE
00110b – 01111b
Reserved
2
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
0
2.1
1
1
1
0
1
2.2
1
1
1
0
0
2.3
1
1
0
1
1
2.4
1
1
0
1
0
2.5
1
1
0
0
1
2.6
1
1
0
0
0
2.7
1
0
1
1
1
2.8
3,5
1
0
1
1
0
2.9
1
0
1
0
1
3.0
1
0
1
0
0
3.1
1
0
0
1
1
3.2
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5
1
1
1
1
1
No core
4, 6
NOTES:
1.
0 = processor pin connected to VSS, 1 = Open on processor; may be pulled up to TTL VIH on baseboard. See the VRM 8.3 DC–DC
Converter Design Guidelines and/or the VRM 8.3 DC–DC Converter Design Guidelines .
Converter Design Guidelines and/or the VRM 8.3 DC–DC Converter Design Guidelines .
2.
VRM output should be disabled for VCC_CORE values less than 1.80V.
3.
Required for 2.8V Pentium® III Xeon™ processors.
4.
The Pentium® III Xeon™ processor at 600 MHz+ does not require an L2 voltage supply. When installing Pentium III Xeon processor
at 600 MHz+, the VCC_L2 and VID_L2 lines will be ”open” on the cartridge.
at 600 MHz+, the VCC_L2 and VID_L2 lines will be ”open” on the cartridge.
5.
This VID setting can be used in combination with HV_EN# pin (A3) for differentiating 2.8V Pentium Xeon processor from 5/12V
Pentium III Xeon processor cartridges.
Pentium III Xeon processor cartridges.
6.
The 5/12V Pentium® III Xeon™ processor does not require a VRM. When installing a 5/12V Pentium III Xeon processor, the
VID_CORE lines will be ”open” on the cartridge.
VID_CORE lines will be ”open” on the cartridge.
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power source of the regulator
only if required by the regulator or external logic monitoring the VID[4:0] signals. The power source chosen to drive/pull up
VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non-zero and the OCVR is enabled.
An invalid VID while the output is coming up could lead to and incorrect voltage above VCC_CORE max. This will prevent
the possibility of the processor supply going above VCC_CORE in the event of a failure in the supply for the VID lines. In
the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10K ohms may be used to connect the VID signals to the converter input.
See the VRM 8.3 DC–DC Converter Design Guidelines for further information.
only if required by the regulator or external logic monitoring the VID[4:0] signals. The power source chosen to drive/pull up
VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non-zero and the OCVR is enabled.
An invalid VID while the output is coming up could lead to and incorrect voltage above VCC_CORE max. This will prevent
the possibility of the processor supply going above VCC_CORE in the event of a failure in the supply for the VID lines. In
the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10K ohms may be used to connect the VID signals to the converter input.
See the VRM 8.3 DC–DC Converter Design Guidelines for further information.