Intel 4 1.60 GHz BX80528JK160G User Manual

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2. The tolerances for this specification have been stated generically to enable the system designer to calculate 

the minimum and maximum values across the range of V

CC

.

3. GTLREF should be generated from V

CC

 by a voltage divider of 1% resistors or 1% matched resistors. Refer 

to the Intel

 850 Chipset Platform Design Guide for implementation details.

4. R

TT

 is the on-die termination resistance measured at V

OL

 of the AGTL+ output driver. Refer to processor I/O 

buffer models for I/V characteristics.

5. COMP resistance must be provided on the system board with 1% resistors. See the Intel

 850 Chipset Platform Design Guide for implementation details.

6. The V

CC

 referred to in these specifications is the instantaneous V

CC

.

7. A COMP Resistance of 43.2 +/- 1% is the preferred value.

The processor System bus timings specified in this section are defined at the processor core 
silicon and are thus not measurable at the processor pins. See Chapter 5.0 for the Pentium 4 
processor pin signal definitions. 

Table 10 through Table 15 list the AC specifications associated with the processor system bus. 

All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise 
specified.

The timings specified in this section should be used in conjunction with the I/O buffer models 
provided by Intel. These I/O buffer models, which include package information, are available for 
the Pentium 4 processor in IBIS format. AGTL+ layout guidelines are also available in the Intel

 850 Chipset Platform Design Guidelines.

Care should be taken to read all notes associated with a particular timing parameter.

1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed 

by the period stability specification (T2).

3. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
4. In this context, period stability is defined as the worst case timing difference between successive crossover 

voltages. In other words, the largest absolute difference between adjacent clock periods must be less than 
the period stability.

5. Slew rate is measured between the 35% and 65% points of the clock swing (V

L

 to V

H

).

System Bus Frequency

100

MHz

T1: BCLK[1:0] Period

10.0

10.2

ns

2

T2: BCLK[1:0] Period Stability

200

ps

3, 4

T3: BCLK[1:0] High Time

3.94

5

6.12

ns

T4: BCLK[1:0] Low Time

3.94

5

6.12

ns

T5: BCLK[1:0] Rise Time

175

700

ps

5

T6: BCLK[1:0] Fall Time

175

700

ps

5