Intel 4 1.60 GHz BX80528JK160G User Manual
Product codes
BX80528JK160G
Intel
®
Pentium
®
4 Processor in the 423-pin Package
23
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
CROSS
) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF
at 2/3 V
CC
± 2%.
5. Specification is for a minimum swing defined between AGTL+ V
IL_MAX
to V
IH_MIN
. This assumes an edge rate
of 0.4 V/ ns to 4.0V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after V
7. This should be measured after V
CC
and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
2. Not 100% tested. Specified by design characterization.
Table 11. System Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3
T10: Common Clock Output Valid Delay
0.20
1.45
ns
4
T11: Common Clock Input Setup Time
0.65
ns
5
T12: Common Clock Input Hold Time
0.40
ns
5
T13: RESET# Pulse Width
1.00
10.00
ms
6, 7, 8
Table 12. System Bus Source Synch AC Specifications AGTL+ Signal Group
T# Parameter
Min
Typ
Max
Unit
Figure
Notes
1,2,3,4
T20: Source Synchronous Data Output
Valid Delay (first data/address only)
Valid Delay (first data/address only)
0.20
1.30
ns
5
T21: T
VBD
: Source Synchronous Data
Output Valid Before Strobe
0.85
ns
5, 8
T22: T
VAD
: Source Synchronous Data
Output Valid After Strobe
0.85
ns
5, 8
T23: T
VBA
: Source Synchronous
Address Output Valid Before Strobe
1.88
ns
5, 8
T24: T
VAA
: Source Synchronous
Address Output Valid After Strobe
1.88
ns
5, 9
T25: T
SUSS
: Source Synchronous Input
Setup Time to Strobe
0.21
ns
6
T26: T
HSS
: Source Synchronous Input
Hold Time to Strobe
0.21
ns
6
T27: T
SUCC
: Source Synchronous Input
Setup Time to BCLK[1:0]
0.65
ns
7
T28: T
FASS
: First Address Strobe to
Second Address Strobe
1/2
BCLK
10
T29: T
FDSS
: First Data Strobe to
Subsequent Strobes
n/4
BCLK
11, 12
T30: Data Strobe ‘n’ (DSTBN#) Output
Valid Delay
Valid Delay
8.80
10.20
ns
13
T31: Address Strobe Output Valid
Delay
Delay
2.27
4.23
ns