Intel III Xeon 900 MHz 80526KY9002M Data Sheet

12

A 2 0 M #

IGNNE#

L I N T 1 / N M I

LINT0/INTR

1K

Ω

2.5 V

Set Ratio:

C R E S E T #

2

2.5 V

000809

NOTES:
1. 

Signal Integrity issues may require this circuit to be modified.

2. 

Current Intel 840 chipsets do not implement the CRESET# signal.

Mixing components of different internal clock frequencies is not supported and has not been validated by Intel. Operating
system support for multi-processing with mixed frequency components should also be considered.

Also, Intel does not support or validate operation of processors with different cache sizes. Intel only supports and
validates multi-processor configurations where all processors operate with the same system bus and core frequencies
and have the same L1 and L2 cache sizes. Similarly, Intel does not support or validate the mixing of Pentium® III Xeon™
processor at 600 MHz+, Pentium® III Xeon™ processor, and Pentium® II Xeon™ processors on the same system bus,
regardless of frequency or L2 cache sizes.

To provide power delivery flexibility, the Pentium III Xeon processor at 600 MHz+ is available in two different input voltage
versions; one version operates at 2.8 Volts and the other at 5 Volts or 12 Volts. As in previous versions of Pentium II Xeon
and Pentium III Xeon processors, the Pentium III Xeon processor at 600 MHz+ contains five voltage identification (VID)
pins, these pins are used on Pentium III Xeon processor at 600 MHz+ for OCVR voltage selection in combination with pin
A3, which incorporates added functionality for power delivery schemes. Further details of this implementation is described
in the Flexible Motherboard Power Distribution & Control for Pentium® III Xeon ™ Processors, Order Number 245245.

The Pentium III Xeon processor at 600 MHz+ incorporates a new pin  (A3, HV_EN#) as a method to identify its ability to
be powered by a 5V or 12V power supply. The HV_EN# signal is used as a way of differentiating a 5/12V Pentium III
Xeon processor cartridge from a 2.8V Pentium III Xeon processor. HV_EN# is tied to VSS (ground) on the 5/12V Pentium
III Xeon processor, and is high impedance (floating) on the 2.8V Pentium III Xeon processor. This is a reserved (no
connect) pin on Pentium® III Xeon™ processors.

Since the L2 Cache is integrated in the core, the Pentium III Xeon processor at 600 MHz+ does not require a VID code to
specify cache voltage (the VID_L2 lines on the Pentium® III Xeon™ processor at 600 MHz+ are all left open on the
cartridge).

 VID_CORE[4:0] controls the voltage supply to the processor, as shown in Table 2. They are not driven signals, but are
either an open circuit or a short circuit to VSS. The combination of opens and shorts defines the voltage required by the
processor (the VID_CORE lines on the 5/12V Pentium® III Xeon™ processor are all left open on the cartridge). The VID
pins support variations in processor core voltages among processors in the SC330 processor family. Table 2 shows the