Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
10
3.3 Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the Pentium® III Xeon™ processor at 600 MHz+ is
capable of generating large average current swings between low and full power states. This causes voltages on power
planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to
ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can
result in timing violations or a reduced lifetime of the component.
capable of generating large average current swings between low and full power states. This causes voltages on power
planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to
ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can
result in timing violations or a reduced lifetime of the component.
3.3.1 VCC_CORE
The power input should provide bulk capacitance with a low Effective Series Resistance (ESR) and the system designer
must also control the interconnect resistance from the regulator (or VRM pins) to the SC330 connector. Simulation is
required for first and second order characterization. Bulk decoupling for the large current swings when the part is
powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the VRM
8.3 DC–DC Converter Design Guidelines . The input to VCC_CORE should be capable of delivering a recommended
minimum dICCCORE/dt while maintaining the required tolerances , each of which is defined in Table 6. See the Flexible
Motherboard Power Distribution & Control for Pentium® III Xeon ™ Processors, Order Number 245245.
must also control the interconnect resistance from the regulator (or VRM pins) to the SC330 connector. Simulation is
required for first and second order characterization. Bulk decoupling for the large current swings when the part is
powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the VRM
8.3 DC–DC Converter Design Guidelines . The input to VCC_CORE should be capable of delivering a recommended
minimum dICCCORE/dt while maintaining the required tolerances , each of which is defined in Table 6. See the Flexible
Motherboard Power Distribution & Control for Pentium® III Xeon ™ Processors, Order Number 245245.
3.3.2 LEVEL 2 CACHE DECOUPLING
The Pentium III Xeon processor at 600 MHz+ does not require the VCC_L2 pins for power.
3.3.3 SYSTEM BUS AGTL+ DECOUPLING
The Pentium III Xeon processor at 600 MHz+ contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling on the system baseboard must be provided to assure proper AGTL+ bus operation. High
frequency decoupling may be necessary at the SC330 connector to further improve signal integrity if noise is picked up at
the connector interface.
substrate; bulk decoupling on the system baseboard must be provided to assure proper AGTL+ bus operation. High
frequency decoupling may be necessary at the SC330 connector to further improve signal integrity if noise is picked up at
the connector interface.
3.4 Clock Frequencies and System Bus Clock Ratios
The Pentium III Xeon processor at 600 MHz+ uses a clock ratio design in which the bus clock is multiplied by a ratio to
produce the processors internal (“core”) clock. The Pentium III Xeon processor at 600 MHz+ begins sampling A20M#,
IGNNE#, LINT[0], and LINT[1] on the inactive-to-active transition of RESET# to determine the core-frequency to bus-
frequency relationship, and the PLL immediately begins to lock on to the input clock. On the active-to-inactive transition of
RESET#, the Pentium III Xeon processor at 600 MHz+ internally latches the inputs to allow the pins to be used for normal
functionality. Effectively, these pins must meet a large setup time (1mS) to the active-to-inactive transition of RESET#
(see RESET# and PWRGD relationship in figure 41). These pins should then be held static for at least 2 bus clocks, but
no longer than 20 bus clocks.
produce the processors internal (“core”) clock. The Pentium III Xeon processor at 600 MHz+ begins sampling A20M#,
IGNNE#, LINT[0], and LINT[1] on the inactive-to-active transition of RESET# to determine the core-frequency to bus-
frequency relationship, and the PLL immediately begins to lock on to the input clock. On the active-to-inactive transition of
RESET#, the Pentium III Xeon processor at 600 MHz+ internally latches the inputs to allow the pins to be used for normal
functionality. Effectively, these pins must meet a large setup time (1mS) to the active-to-inactive transition of RESET#
(see RESET# and PWRGD relationship in figure 41). These pins should then be held static for at least 2 bus clocks, but
no longer than 20 bus clocks.
Table 1. System Bus-to-Core Frequency Ratio Configuration
Ratio of BCLK to
Core Frequency
133 MHz
Target
Frequency
Frequency
EBL PWRUP
Reg[25:22]
LINT[1]
LINT[0]
IGNNE#
A20M#
¼ (Safe-LLLL)
0011
L
L
L
L
2/9
600 MHz
0110
L
H
L
H
1/5
667 MHz
0000
L
L
H
H
2/11
733 MHz
0100
L
H
H
H
1/6
800 MHz
1011
H
L
L
L
2/13
866 MHz
1111
H
H
L
L
1/7
933 MHz
1001
H
L
H
L
2/15
1000 MHz
1101
H
H
H
L
¼ (Safe-HHHH)
1100
H
H
H
H