Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
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5. PROCESSOR FEATURES
5.1 Low Power States and Clock Control
The Pentium® III Xeon™ processor at 600 MHz+ allows the use of Auto HALT, Stop-Grant, and Sleep states
to reduce power consumption by stopping the clock to specific internal sections of the processor, depending
on each particular state. There is no Deep Sleep state on the Pentium III Xeon processor at 600 MHz+. Refer
to for the following sections on low power states for the Pentium III Xeon processor at 600 MHz+.
to reduce power consumption by stopping the clock to specific internal sections of the processor, depending
on each particular state. There is no Deep Sleep state on the Pentium III Xeon processor at 600 MHz+. Refer
to for the following sections on low power states for the Pentium III Xeon processor at 600 MHz+.
For the processor to fully realize the low current consumption of the Stop Grant, and Sleep states, an MSR bit
must be set. For the MSR at 02AH (Hex), bit 26 must be set to a ‘1’ (power on default is a ‘0’) for the
processor to stop all internal clocks during these modes. For more information, see the Pentium II processor
Developer's Manual (Order Number 243502). Due to not being able to recognize bus transactions during
Sleep state, SMP systems are not allowed to have one or more processors in Sleep state and other
processors in Normal or Stop Grant states simultaneously.
must be set. For the MSR at 02AH (Hex), bit 26 must be set to a ‘1’ (power on default is a ‘0’) for the
processor to stop all internal clocks during these modes. For more information, see the Pentium II processor
Developer's Manual (Order Number 243502). Due to not being able to recognize bus transactions during
Sleep state, SMP systems are not allowed to have one or more processors in Sleep state and other
processors in Normal or Stop Grant states simultaneously.
5.1.1
NORMAL STATE — STATE 1
This is the normal operating state for the processor.
5.1.2
AUTO HALT POWER DOWN STATE — STATE 2
Auto HALT is a low power state entered when the Pentium III Xeon processor at 600 MHz+ executes the
HALT instruction. The processor will issue a normal HALT bus cycle on BE[7:0]# and REQ[4:0]# when
entering this state. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#,
INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
HALT instruction. The processor will issue a normal HALT bus cycle on BE[7:0]# and REQ[4:0]# when
entering this state. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#,
INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
SMI# will cause the processor to execute the SMI handler. The return from the SMI handler can be to either
Normal Mode or the Auto HALT Power Down state. See Chapter 11 in the Intel Architecture Software
Developer’s Manual Volume 3: System Programming.
Normal Mode or the Auto HALT Power Down state. See Chapter 11 in the Intel Architecture Software
Developer’s Manual Volume 3: System Programming.
FLUSH# will be serviced during Auto HALT state. The on-chip first level caches and external second level
cache will be flushed and the processor will return to the Auto HALT state.
cache will be flushed and the processor will return to the Auto HALT state.
A20M# will be serviced during Auto HALT state; the processor will mask physical address bit 20 (A20#) before
any look-up in either the on-chip first level caches or external second level cache, and before a read/write
transaction is driven on the bus.
any look-up in either the on-chip first level caches or external second level cache, and before a read/write
transaction is driven on the bus.
The system can generate a STPCLK# while the processor is in the Auto HALT Power Down state. The
processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state. If the
processor enters the Stop Grant state from the Auto HALT state, the STPCLK# signal must be deasserted
before any interrupts are serviced (see below). When the system deasserts the STPCLK# interrupt signal, the
processor will return execution to the HALT state. The processor will not generate a new HALT bus cycle
when it re-enters the HALT state from the Stop Grant state.
processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state. If the
processor enters the Stop Grant state from the Auto HALT state, the STPCLK# signal must be deasserted
before any interrupts are serviced (see below). When the system deasserts the STPCLK# interrupt signal, the
processor will return execution to the HALT state. The processor will not generate a new HALT bus cycle
when it re-enters the HALT state from the Stop Grant state.