Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
46
5.2.2
SCRATCH EEPROM
Also available on the SMBus is an EEPROM that may be used for other data at the system or processor
vendor’s discretion. This device has a pull-down on the WP control pin through a 10K
vendor’s discretion. This device has a pull-down on the WP control pin through a 10K
Ω
resistor, as
implemented on all previous Pentium® II Xeon™ and Pentium III Xeon processors. This will allow the OEM
EEPROM to be programmed in systems with no manipulation of this signal. Once programmed, the data in
this OEM EEPROM can be write protected by asserting the active-high WP signal. The Scratch EEPROM is a
1024 bit part.
EEPROM to be programmed in systems with no manipulation of this signal. Once programmed, the data in
this OEM EEPROM can be write protected by asserting the active-high WP signal. The Scratch EEPROM is a
1024 bit part.
5.2.3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS
TRANSACTIONS
Four SMBus packet types are associated with the PIROM and Scratch EEPROM. Each of these packet
transfers provides a device select address and read/write bit. The remaining parts of the transfer vary. Two of
the packets, Send Byte and Receive Byte, transfer one additional byte after the device select. The other two
packets, Write Byte and Read Byte, transfer two additional bytes after the device select. By using these four
transfer types, complete access to the EEPROMs is possible.
transfers provides a device select address and read/write bit. The remaining parts of the transfer vary. Two of
the packets, Send Byte and Receive Byte, transfer one additional byte after the device select. The other two
packets, Write Byte and Read Byte, transfer two additional bytes after the device select. By using these four
transfer types, complete access to the EEPROMs is possible.
Send Byte loads an address into the memory device that is used for subsequent access. Send Byte does not
change the contents of the EEPROM, just the address pointer within it. See Table 27 and explanation below.
change the contents of the EEPROM, just the address pointer within it. See Table 27 and explanation below.
Receive Byte gets a byte of data from the memory device. It uses an address already loaded into the
EEPROM device and returns the byte at that address. Repetitive use of Receive Byte to access an address
range is possible. See Table 28 and explanation below. Write Byte transfers both an address and data byte
into the memory device. It is a stand-alone write cycle. See Table 29. Read Byte transfers an address and
gets a byte of data from the memory device. It is a stand alone read cycle. See Table 30.
EEPROM device and returns the byte at that address. Repetitive use of Receive Byte to access an address
range is possible. See Table 28 and explanation below. Write Byte transfers both an address and data byte
into the memory device. It is a stand-alone write cycle. See Table 29. Read Byte transfers an address and
gets a byte of data from the memory device. It is a stand alone read cycle. See Table 30.
Both ROMs respond to SMBus packet types Send Byte, Receive Byte, and Read Byte. The Scratch EEPROM
additionally responds to the packet type Write Byte.
additionally responds to the packet type Write Byte.
The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus
specification. However, by use of the four transfers described above, all transfer requirements to these
devices can be achieved.
specification. However, by use of the four transfers described above, all transfer requirements to these
devices can be achieved.
NOTE: In Tables 27 - 30 below:
S indicates a start condition (SDA falling while SCK high)
P indicates a stop condition (SDA rising while SCK high)
R/W* indicates a read/write not signal (1 = read, 0 = write)
A* indicates an acknowledge* signal, (0 = acknowledge, 1 = not acknowledge).
The shaded portions of the following Tables indicate that the SMBus slave device is driving the bus , while the
clear portions indicate that the SMBus master device under control of the host is driving the bus .
The shaded portions of the following Tables indicate that the SMBus slave device is driving the bus , while the
clear portions indicate that the SMBus master device under control of the host is driving the bus .
Table 27. Send Byte SMBus Packet
S
Device
Address
R/
W*
A*
Data
A*
P
1
7 bits
0
0
8 bits
0
1
Table 27 outlines the Send Byte packet, which provides an address to the device for later use. The start
condition is followed by a device select field and a write bit, which are acknowledged by the device. The
following data byte is really an address, which is also acknowledged by the device. Finally the stop condition
is signaled.
condition is followed by a device select field and a write bit, which are acknowledged by the device. The
following data byte is really an address, which is also acknowledged by the device. Finally the stop condition
is signaled.