Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
47
Table 28. Receive Byte SMBus Packet
S
Device
Address
R/
W*
A*
Data
A*
P
1
7 bits
1
0
8 bits
1
1
Table 28 diagrams the Receive Byte packet that performs as a current address read. The start condition is
followed by a device select address field and a read flag. The device decodes its address and drives
acknowledge low. The data is returned by the device and the transfer is terminated by the controller providing
negative acknowledge and a stop. Note that there is no data address provided, only the device address. The
EEPROM internal address counter keeps track of the address accessed during the last read or write
operation, incremented by one. Repeated current address reads will receive data from consecutive
addresses. Address roll over will occur when the last byte of the device has been read. In this event it will roll
over to the first byte of the device.
followed by a device select address field and a read flag. The device decodes its address and drives
acknowledge low. The data is returned by the device and the transfer is terminated by the controller providing
negative acknowledge and a stop. Note that there is no data address provided, only the device address. The
EEPROM internal address counter keeps track of the address accessed during the last read or write
operation, incremented by one. Repeated current address reads will receive data from consecutive
addresses. Address roll over will occur when the last byte of the device has been read. In this event it will roll
over to the first byte of the device.
Table 29. Write Byte SMBus Packet
S
Device
Address
R/
W*
A*
Data
Address
A*
Data
A*
P
1
7 bits
0
0
8 bits
0
8 bits
0
1
Table 29 diagrams the Write Byte packet. This is effectively a Random Address Write function. The device
select address, data offset address and write data are provided within the packet. The device address is
followed by a write flag. The EEPROM device drives each of the three acknowledge pulses . After the Write
Byte packet is received the Scratch EEPROM device enters a timed writing mode during which it will not
respond to further transfers. This timed writing mode will be approximately 10 milliseconds in duration.
select address, data offset address and write data are provided within the packet. The device address is
followed by a write flag. The EEPROM device drives each of the three acknowledge pulses . After the Write
Byte packet is received the Scratch EEPROM device enters a timed writing mode during which it will not
respond to further transfers. This timed writing mode will be approximately 10 milliseconds in duration.
Table 30. Read Byte SMBus Packet
S
Device
Address
R/
W*
A*
Data
Address
A
*
S
Device
Address
R/
W*
A*
Data
A*
P
1
7 bits
0
0
8 bits
0
1
7 bits
1
0
8 bits
1
1
5.2.4 Table 30 illustrates the Read Byte packet. This is effectively a Random Address Read function.
This is actually two consecutive SMBus transfers, an address write followed by a current address
read from the same device. In the address write portion, both device address and data address
are acknowledged by the EEPROM. A second start condition then occurs, followed by a receive
byte read such as diagrammed above. From the programming perspective, this may be treated as
are acknowledged by the EEPROM. A second start condition then occurs, followed by a receive
byte read such as diagrammed above. From the programming perspective, this may be treated as
two separate transfers.
THERMAL SENSOR
The Pentium® III Xeon™ processor at 600 MHz+ thermal sensor provides a means of acquiring thermal data
from the processor with an exceptional degree of precision. The thermal sensor is composed of control logic,
SMBus interface logic, a precision analog-to-digital converter, and a precision current source. The thermal
sensor drives a small current through the p-n junction of a thermal diode located on the same silicon die as
the processor core. The forward bias voltage generated across the thermal diode is sensed and the precision
A/D converter derives a single byte of thermal reference data, or a “thermal byte reading.” System
management software running on the processor or on a microcontroller can acquire the data from the thermal
sensor to thermally manage the system.
from the processor with an exceptional degree of precision. The thermal sensor is composed of control logic,
SMBus interface logic, a precision analog-to-digital converter, and a precision current source. The thermal
sensor drives a small current through the p-n junction of a thermal diode located on the same silicon die as
the processor core. The forward bias voltage generated across the thermal diode is sensed and the precision
A/D converter derives a single byte of thermal reference data, or a “thermal byte reading.” System
management software running on the processor or on a microcontroller can acquire the data from the thermal
sensor to thermally manage the system.
Upper and lower thermal reference thresholds can be individually programmed for the thermal diode.
Comparator circuits sample the register where the single byte of thermal data (thermal byte reading) is stored.
These circuits compare the single byte result against programmable threshold bytes. The alert signal on the
Pentium® III Xeon™ processor at 600 MHz+ SMBus (SMBALERT#) will assert when either threshold is
crossed.
Comparator circuits sample the register where the single byte of thermal data (thermal byte reading) is stored.
These circuits compare the single byte result against programmable threshold bytes. The alert signal on the
Pentium® III Xeon™ processor at 600 MHz+ SMBus (SMBALERT#) will assert when either threshold is
crossed.
To increase the usefulness of the thermal diode and thermal sensor, Intel has added a new procedure to the
manufacturing and test flow of the Pentium III Xeon processor at 600 MHz+. This procedure determines the
Thermal Reference Byte and programs it into the processor Information ROM. The Thermal Reference Byte is
manufacturing and test flow of the Pentium III Xeon processor at 600 MHz+. This procedure determines the
Thermal Reference Byte and programs it into the processor Information ROM. The Thermal Reference Byte is