Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
52
The thermal sensor latches the SA1 and SA2 signals at power up. System designers should ensure that these
signals are at valid input levels before the thermal sensor powers up. This should be done by pulling the pins
signals are at valid input levels before the thermal sensor powers up. This should be done by pulling the pins
to VCCSMB or VSS via a 1K-ohm or smaller resistor. Additionally, SA2 may be left unconnected to achieve
the tri-state or “Z” state. If the designer desires to drive the SA1 or SA2 pin with logic the designer must
ensure that the pins are at valid input levels (see Table 9) before VCCSMB begins to ramp. The system
designer must also ensure that their particular system implementation does not add excessive capacitance
(>50 pF) to the address inputs. Excess capacitance at the address inputs may cause address recognition
problems .
the tri-state or “Z” state. If the designer desires to drive the SA1 or SA2 pin with logic the designer must
ensure that the pins are at valid input levels (see Table 9) before VCCSMB begins to ramp. The system
designer must also ensure that their particular system implementation does not add excessive capacitance
(>50 pF) to the address inputs. Excess capacitance at the address inputs may cause address recognition
problems .
Figure 16 shows a logical diagram of the pin connections. Table 40 and Table 41 describe the address pin
connections and how they affect the addressing of the devices.
connections and how they affect the addressing of the devices.
Table 40. Thermal Sensor SMBus Addressing
Address (Hex)
Upper Address
1
Slot Select
8-bit Address Word on Serial Bus
SA1
SA2
b[7:0]
3Xh
0011
0
0
0011000Xb
0011
1
0
0011010Xb
5Xh
0101
0
Z
2
0101001Xb
0101
1
Z
2
0101011Xb
9Xh
1001
0
1
1001100Xb
1001
1
1
1001110Xb
NOTES:
1.
Upper address bits are decoded in conjunction with the select pins.
2.
A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note that system management software must be aware of the slot number-dependent changes in the address
for the thermal sensor.
for the thermal sensor.
Table 41. Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Slot Select
Memory
Device
Select
R/W
Device Addressed
bits 7-4
(SA1)
bit 3
(SA0)
bit 2
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
Scratch EEPROM 1
A2h/A3h
1010
0
0
1
X
processor Information ROM 1
A4h/A5h
1010
0
1
0
X
Scratch EEPROM 2
A6h/A7h
1010
0
1
1
X
processor Information ROM 2
A8h/A9h
1010
1
0
0
X
Scratch EEPROM 3
AAh/ABh
1010
1
0
1
X
processor Information ROM 3
ACh/ADh
1010
1
1
0
X
Scratch EEPROM 4
AEh/AFh
1010
1
1
1
X
processor Information ROM 4
Though this addressing scheme is targeted for up to 4-way MP systems, more processors can be supported
by using a multiplexed (or separate) SMBus implementation.
by using a multiplexed (or separate) SMBus implementation.