Intel III Xeon 900 MHz 80526KY9002M Data Sheet

77

TDO

10

Test data output signal
from last component in

boundary scan chain of

MP cluster to ITP; test
output is read serially.

Add 150-ohm  pull-up resistor

(to VCC_TAP).

Design pull-ups to route around

empty processor sockets (so

resistors are not in parallel).

Operates synchronously with TCK.

Each Pentium® III Xeon™

processor at 600 MHz+ has a   25

ohm driver.

DBINST#

11

Indicates to target system

that the ITP is installed.

Add ~10K  ohm pull-up resistor.

Not required if boundary scan is not

used in target system.

TRST#

12

Test reset signal from ITP

to MP cluster, used to

reset TAP logic.

Add ~680  ohm pull-down.

To disable TAP reset if ITP not

installed.

Asynchronous input signal.

BSEN#

14

Informs target system that

ITP is using boundary

scan.

Not required if boundary scan is not

used in target system.

PREQ0#

16

PREQ0# signal, driven by

ITP, makes requests to P0

to enter debug.

Add 150 to 330  ohm pull-up

resistor (to VCC_TAP).

PRDY0#

18

PRDY0# signal, driven by
P0, informs ITP that P0 is

ready for debug.

Terminate

2

 signal properly at

the debug port.

Debug port must be at the end

of the signal trace.

Connected to high-speed

comparator (biased at 2/3 of the

level found at the POWERON pin)
on the ITP buffer board. Additional

load does not change timing

calculations for the processor bus

agents if routed properly.

PREQ1#

20

PREQ1# signal from ITP to

P1.

Add 150 to 330  ohm pull-up

resistor (to VCC_TAP)

PRDY1#

22

PRDY1# signal from P1 to

ITP.

Terminate

2

 signal properly at

the debug port.

Debug port must be at the end

of the signal trace.

Connected to high-speed

comparator (biased at 2/3 of the

level found at the POWERON pin)
on the ITP buffer board. Additional

load does not change timing

calculations for the processor bus

agents.

PREQ2#

24

PREQ2# signal from ITP to

P2.

Add 150 to 330  ohm pull-up

resistor (to VCC_TAP).

PRDY2#

26

PRDY2# signal from ITP to

P2.

Terminate

2

 signal properly at

the debug port.

Debug port must be at the end

of the signal trace.

Connected to high-speed

comparator (biased at 2/3 of the

level found at the POWERON pin)
on the ITP buffer board. Additional

load does not change timing

calculations for the processor bus

agents if routed properly.

PREQ3#

28

PREQ3# signal from ITP to

P3.

Add 150 to 330  ohm pull-up

resistor (to VCC_TAP).

PRDY3#

30

PRDY3# signal from ITP to

P3.

Terminate

2

 signal properly at

the debug port.

Debug port must be at the end

of the signal trace.

Connected to high-speed

comparator (biased at 2/3 of the

level found at the POWERON pin)
on the ITP buffer board. Additional

load does not change timing

calculations for the processor bus

agents if routed properly.

BCLK

29

Bus clock from the MP

cluster.

Use a separate driver to drive

signal to the debug port.

Must be connected to support

future steppings of the

A separate driver should be used to

avoid loading issues associated with
having the ITP either installed or not

installed.