Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
INTEGRATION TOOLS
80
Figure 31. TCK with individual buffering scheme
The ITP buffer board drives the TCK signal through the debug port, to the buffered device(s).
NOTE
The buffer rise and fall edge rates should NOT be FASTER than 3nS. Edge rates faster than this in
the system can contribute to signal reflections that endanger ITP compatibility with the target
system.
the system can contribute to signal reflections that endanger ITP compatibility with the target
system.
A low voltage buffer capable of driving 2.5V outputs such as a 74LVQ244 is suggested to
eliminate the need for attenuation.
eliminate the need for attenuation.
Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast.
The pull-up resistor to 2.5V keeps the TCK signal from floating when the ITP is not connected. The value of
this resistor should be such that the ITP can still drive the signal low (1K). The trace lengths from the buffer to
each of the agents should also be kept at a minimum to ensure good signal integrity.
this resistor should be such that the ITP can still drive the signal low (1K). The trace lengths from the buffer to
each of the agents should also be kept at a minimum to ensure good signal integrity.
8.1.7 Using the TAP to Communicate to the processor
An ITP communicates to the Pentium® III Xeon™ processor at 600 MHz+ by stopping its execution, and
sending/receiving messages over boundary scan pins. As long as each processor is tied into the system
boundary scan chain, the ITP can communicate with it. In the simplest case, the processors are back to back
in the scan chain, with the boundary scan input (TDI) of the first processor connected up directly to the pin
labeled TDI on the debug port and the boundary scan output of the last processor connected up to the pin
labeled TDO on the debug port as shown in Figure 32.
sending/receiving messages over boundary scan pins. As long as each processor is tied into the system
boundary scan chain, the ITP can communicate with it. In the simplest case, the processors are back to back
in the scan chain, with the boundary scan input (TDI) of the first processor connected up directly to the pin
labeled TDI on the debug port and the boundary scan output of the last processor connected up to the pin
labeled TDO on the debug port as shown in Figure 32.
processor
#1
processor
#2
To each device, other
JTAG
...
TCK
2.5V
Buffers
74LVQ244
Type
Pull up
Resistor
2.5V
56
pF
pF
56
pF
56
pF
100
nH
100
nH
100
nH