Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
93
10.1.21 FERR# (O)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR#
is similar to the ERROR# signal on the Intel387™ coprocessor, and is included for compatibility with systems using DOS-
type floating-point error reporting.
is similar to the ERROR# signal on the Intel387™ coprocessor, and is included for compatibility with systems using DOS-
type floating-point error reporting.
10.1.22 FLUSH# (I)
When the FLUSH# input signal is asserted, processors write back all data in the Modified state from their internal caches
and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal remains asserted.
and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power-on configuration.
See Pentium II processor Developer’s Manual for details.
See Pentium II processor Developer’s Manual for details.
10.1.23 HIT# (I/O), HITM# (I/O)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the
appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+ system bus agents. Any such agent may assert both
HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+ system bus agents. Any such agent may assert both
HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
10.1.24 HV_EN# (O)
The HV_EN# signal is used as a way of differentiating a 5/12V Pentium III Xeon processor cartridge from a 2.8V Pentium
III Xeon processor. HV_EN# is tied to VSS (ground) on the 5/12V Pentium III Xeon processor, and is high impedance
(floating) on the 2.8V Pentium III Xeon processor. This is a reserved (no connect) pin on Pentium® III Xeon™ processors.
III Xeon processor. HV_EN# is tied to VSS (ground) on the 5/12V Pentium III Xeon processor, and is high impedance
(floating) on the 2.8V Pentium III Xeon processor. This is a reserved (no connect) pin on Pentium® III Xeon™ processors.
10.1.25 IERR# (O)
The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is
usually accompanied by a SHUTDOWN transaction on the Pentium III Xeon processor at 600 MHz+ system bus. This
transaction may optionally be converted to an external error signal (e.g. NMI) by system core logic. The processor will
keep IERR# asserted until it is handled in software, or with the assertion of RESET#, BINIT#, or INIT#.
usually accompanied by a SHUTDOWN transaction on the Pentium III Xeon processor at 600 MHz+ system bus. This
transaction may optionally be converted to an external error signal (e.g. NMI) by system core logic. The processor will
keep IERR# asserted until it is handled in software, or with the assertion of RESET#, BINIT#, or INIT#.
10.1.26 IGNNE# (I)
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to
execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-
control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE
bit in control register 0 is set.
execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-
control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE
bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
During active RESET#, the Pentium III Xeon processor at 600 MHz+ begins sampling the A20M#, IGNNE# , and
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-
inactive transition of RESET#, the Pentium III Xeon processor at 600 MHz+ latches these signals and freezes the
frequency ratio internally. System logic must then release these signals for normal operation.
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-
inactive transition of RESET#, the Pentium III Xeon processor at 600 MHz+ latches these signals and freezes the
frequency ratio internally. System logic must then release these signals for normal operation.
10.1.27 INIT# (I)
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal
(L1 or L2) caches or floating-point registers. Each processor then begins execution at the power-on reset vector
configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
INIT# is an asynchronous signal and must connect the appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+
system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes
its Built-In Self-Test (BIST).
(L1 or L2) caches or floating-point registers. Each processor then begins execution at the power-on reset vector
configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
INIT# is an asynchronous signal and must connect the appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+
system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes
its Built-In Self-Test (BIST).