Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
94
10.1.28 INTR - see LINT[0]
10.1.29 LINT[1:0] (I)
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
During active RESET#, the Pentium III Xeon processor at 600 MHz+ begins sampling the A20M#, IGNNE# , and
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-
inactive transition of RESET#, the Pentium III Xeon processor at 600 MHz+ samples these signals and latches the
frequency ratio internally. System logic must then release these signals for normal operation.
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-
inactive transition of RESET#, the Pentium III Xeon processor at 600 MHz+ samples these signals and latches the
frequency ratio internally. System logic must then release these signals for normal operation.
10.1.30 LOCK# (I/O)
The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. For a locked sequence of
transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. For a locked sequence of
transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium III Xeon processor at 600 MHz+ system
bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the Pentium III
Xeon processor at 600 MHz+ system bus throughout the bus locked operation and ensure the atomicity of lock.
bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the Pentium III
Xeon processor at 600 MHz+ system bus throughout the bus locked operation and ensure the atomicity of lock.
10.1.31 L2_SENSE
On Pentium III Xeon cartridges, L2_SENSE is routed from the edge of the connector pin B57 to the VL2 power plane. It
allows monitoring the delivery of VCC_L2 voltage at the L2 array device for the Pentium III Xeon processor. This line is
NOT specified in legacy systems and is not recommended to be connected in Pentium III Xeon processor at 600 MHz+
only systems.
allows monitoring the delivery of VCC_L2 voltage at the L2 array device for the Pentium III Xeon processor. This line is
NOT specified in legacy systems and is not recommended to be connected in Pentium III Xeon processor at 600 MHz+
only systems.
Systems that rely on remote sensing of VCC_L2 need to guarantee this requirement is met at the VRM sense line
regardless of core feedback
.
10.1.32 OCVR_EN (I)
This signal is the output enable for the internal cartridge voltage regulator. Driving this Low will inactivate the outputs of
the OCVR. This is an open drain signal referenced high to +5V through a 10K ohm resistor within the cartridge to
activate the VRM when not driven low (this to satisfy legacy requirements). Refer to Figure 41 and Figure 42 For PWRGD
relationships at Power up.
the OCVR. This is an open drain signal referenced high to +5V through a 10K ohm resistor within the cartridge to
activate the VRM when not driven low (this to satisfy legacy requirements). Refer to Figure 41 and Figure 42 For PWRGD
relationships at Power up.
10.1.33 OCVR_OK(O)
This is an open drain compatible output from the On-Cartridge Voltage Regulator Module (OCVR) indicating that its
outputs are enabled and operating within specifications. This signal is referenced to VCC_SMB (+3.3V) through a 10K
ohm resistor, and should be used in conjunction with an equivalent signal from the host power system to generate the
CORE_PWRGD signals for the processor cores. Refer to Figure 41 and Figure for PWRGD relationships at Power up.
PWRGD assertion must lag OCVR_OK assertion.
outputs are enabled and operating within specifications. This signal is referenced to VCC_SMB (+3.3V) through a 10K
ohm resistor, and should be used in conjunction with an equivalent signal from the host power system to generate the
CORE_PWRGD signals for the processor cores. Refer to Figure 41 and Figure for PWRGD relationships at Power up.
PWRGD assertion must lag OCVR_OK assertion.
10.1.34 NMI - See LINT[1]
10.1.35 PICCLK (I)
The PICCLK (APIC Clock) signal is a 2.5V tolerant input clock to the processor and core logic or I/O APIC that is required
for operation of all processors, core logic, and I/O APIC components on the APIC bus.
for operation of all processors, core logic, and I/O APIC components on the APIC bus.