Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
97
Figure 42. PWRGD Implementation
10.1.41 REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all Pentium® III Xeon™ processor at
600 MHz+ system bus agents. They are asserted by the current bus owner over two clock cycles to define the currently
active transaction type.
600 MHz+ system bus agents. They are asserted by the current bus owner over two clock cycles to define the currently
active transaction type.
10.1.42 RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing
back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset,
RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this
de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified. On
observing active RESET#, all Pentium III Xeon processor at 600 MHz+ system bus agents will deassert their outputs
within two clocks.
back any of their contents. RESET# must remain active for one microsecond for a "warm" reset; for a power-on reset,
RESET# must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted; until this
de-assertion of RESET# occurs, all outputs from the processor are indeterminate unless otherwise specified. On
observing active RESET#, all Pentium III Xeon processor at 600 MHz+ system bus agents will deassert their outputs
within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Pentium II processor Developer’s Manual .
configuration options are described in the Pentium II processor Developer’s Manual .
The processor may have its outputs tri-stated via power-on configuration. Otherwise, if INIT# is sampled active during the
active-to-inactive transition of RESET#, the processor will execute its Built-In Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect
the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents.
active-to-inactive transition of RESET#, the processor will execute its Built-In Self-Test (BIST). Whether or not BIST is
executed, the processor will begin program execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect
the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents.
10.1.43 RP# (I/O)
The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on ADS# and REQ[4:0]#.
It must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. A correct parity
signal is high if an even number of covered signals is low and low if an odd number of covered signals are low. This
definition allows parity to be high when all covered signals are high.
It must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system bus agents. A correct parity
signal is high if an even number of covered signals is low and low if an odd number of covered signals are low. This
definition allows parity to be high when all covered signals are high.
10.1.44 RS[2:0]# (I)
+5V
OCVR_EN
OCVR
OCVR_OK
OCVR_OK
CPU_PWR_GD
OCVR_EN
5V
PWR_GD_PS
Vcc_smb(3.3V)
5V
CPU_PWRGD
Other PS’s,
VRMs, OCVRs
with
open-drain
PWR_GDs
PWR_GDs
VRM
PWRGD
OUTEN
CPU_RESET#
Delay
Logic
Logic
Reset Logic
3V->5V
buffer
(7408)
buffer
(7408)
3.3V
Pull-up for Pentium® III Xeon™ Processor
3.3V
Processor
Core