Intel III Xeon 900 MHz 80526KY9002M Data Sheet
Product codes
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
99
Processor
Pin Location
Pin Name
Functionality
A7
SELFSB1
Output,
Frequency
Detect
Frequency
Detect
Pentium® III Xeon™
processor at 600 MHz+
processor at 600 MHz+
A9
SELFSB0
Input,
Frequency
Selection.
Frequency
Selection.
SELFSB1: Output, (Frequency Detect).
133Mhz = N/C
SELFSB0:
Pentium III Xeon processor at 600 MHz+ : Input; (Frequency Select).
133MHz = Pull up to 2.5V
Table 52. Description of SELFSB pins
10.1.48 SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop Grant state, causes processors to enter the Sleep state. During Sleep
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating. processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of
the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units.
state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still
operating. processors in this state will not recognize snoops or interrupts. The processor will recognize only assertions of
the SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core units.
10.1.49 SMBALERT# (O)
SMBALERT# is an asynchronous interrupt line associated with the SMBus Thermal Sensor device.
10.1.50 SMBCLK (I)
The SMBCLK (SMBus Clock) signal is an input clock to the system management logic that is required for operation of the
system management features of the Pentium III Xeon processor at 600 MHz+. This clock is asynchronous to other clocks
to the processor.
system management features of the Pentium III Xeon processor at 600 MHz+. This clock is asynchronous to other clocks
to the processor.
10.1.51 SMBDAT (I/O)
The SMBDAT (SMBus DATa) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for
transferring data between SMBus devices.
transferring data between SMBus devices.
10.1.52 SMI# (I)
The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
10.1.53 STPCLK# (I)