Intel 1.40 GHz RH80532NC017256 Data Sheet

298517-006 Datasheet 

87 

a resistor divider to generate 1.25 V from the 2.5-V supply.  A minimum of 1-µF decoupling capacitance 
is recommended on CLKREF. On systems with Differential Clocking, the CLKREF pin functions as the 
BCLK# input. 

The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the CMOS 
input buffers. CMOSREF must be generated from a stable 1.5V supply (830 chipset family), 2.5 V 
(440MX chipset family) and must meet the VCMOSREF specification. The same 1.5 V (830 chipset 
family) or 2.5 V (440MX chipset family) supply should be used to power the chipset CMOS I/O buffers 
that drive the CMOS signals.  The Thevenin equivalent impedance of the VCMOSREF generation 
circuits must be less than 0.5 KΩ/1 KΩ (i.e., top resistor 500 Ω, bottom resistor 1 KΩ) for the Intel 830 
Chipset family. The Thevenin equivalent impedance of the VCMOSREF generation circuits must be less 
than 0.75 KΩ/0.5 KΩ (i.e., top resistor 750 Ω, bottom resistor 500 Ω) for the Intel 440MX chipset 
family. 

The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between both 
system bus agents, and must be connected to the appropriate pins/balls on both agents. The data driver 
asserts DRDY# to indicate a valid data transfer.  

The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system 
bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal 
must be connected to the appropriate pins/balls on both agents on the system bus. 

The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be guaranteed 
in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory agent 
or I/O agent. This signal must be connected to the appropriate pins/balls on both agents on the system 
bus. 

The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus. 
They are driven by the agent responsible for driving D[63:0]#, and must be connected to the appropriate 
pins/balls on both agents on the system bus if they are used. During power-on configuration, DEP[7:0]# 
signals can be enabled for ECC checking or disabled for no checking. 

The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid 
data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks. This 
signal must be connected to the appropriate pins/balls on both agents on the system bus. 

The DPSLP# (Deep Sleep) signal, when asserted in the Quick Start state, causes the processor to enter 
the Deep Sleep state.  In order to return to the Quick Start state BCLK, BCLK# must be running and the 
DPSLP# pin must be deasserted.