Intel 1.40 GHz RH80532NC017256 Data Sheet

298517-006 Datasheet 

89 

The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes the 
LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the EFLAGS 
register. If the IF bit is set, the processor vectors to the interrupt handler after completing the current 
instruction execution. Upon recognizing the interrupt request, the processor issues a single Interrupt 
Acknowledge (INTA) bus transaction. INTR must remain active until the INTA bus transaction to 
guarantee its recognition. 

The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of all 
APIC bus agents, including the processor and the system logic or I/O APIC component. When APIC is 
disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes 
NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the same signals for the 
Pentium processor. Both signals are asynchronous inputs.  

Both of these signals must be software configured by programming the APIC register space to be used 
either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then LINT[1:0] is the 
default configuration. 

The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur atomically. 
This signal must be connected to the appropriate pins/balls on both agents on the system bus. For a 
locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction through 
the end of the last transaction.  

When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes LOCK# 
deasserted. This enables the processor to retain bus ownership throughout the bus locked operation and 
guarantee the atomicity of lock.  

The NCTRL signal provides the AGTL pull down impedance control.  The processor samples this input 
to determine the N-channel pull-down device strength when it is the driving agent.  An external 14 ohm 
(1% tolerance) pull-up resistor to V

CCT

 is required for this signal. Please refer to platform design guide 

for implementation details. 

The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI 
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an 
internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If 
NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized 
after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending. 
NMI is rising edge sensitive.  

The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC that is 
required for operation of the processor, system logic, and I/O APIC components on the APIC bus.