Intel 1.70 GHz RH80532NC029256 Data Sheet

298517-006 Datasheet 

21 

other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any devices with 3.3-
V or 5.0-V JTAG interfaces within the system. A translation buffer should be used to reduce the TDO 
output voltage of the last 3.3/5.0 V device down to the 1.5-V range that the Mobile Intel Celeron 
Processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level. 

A Debug Port and connector may be placed at the start and end of the JTAG chain containing the 
processor, with TDI to the first component coming from the Debug Port and TDO from the last 
component going to the Debug Port. There are no requirements for placing the Mobile Intel Celeron 
Processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP 
signals. 

The Mobile Intel Celeron Processor does not support catastrophic thermal protection or the 
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the system 
against excessive temperatures. If the external thermal sensor detects a processor junction temperature of 
101 

°C (maximum), both the V

CC

 and V

CCT

 supplies to the processor must be reduced to at least 50% of 

the nominal values within 500 ms and are recommended to be turned off completely within 1 second to 
prevent damage to the processor. Processor temperature must be monitored in all states including low 
power states. 

All signals named NC must be unconnected. Unused AGTL inputs, outputs, and bi-directional signals 
should be unconnected. Unused CMOS active low inputs should be connected to 1.5 V and unused 
active high inputs should be connected to V

SS

. Unused Open-drain outputs should be unconnected. When 

tying any signal to power or ground, a resistor will allow for system testability. For unused signals, Intel 
suggests that 1.5-k

Ω resistors are used for pull-ups and 1.0-kΩ resistors are used for pull-downs.  

PICCLK must be driven with a clock that meets specification and the PICD[1:0] signals must be pulled 
up separately to 1.5 V with 150-

Ω resistors, even if the local APIC is not used. 

If the TAP signals are not used then the inputs should be pulled to ground with 1-k

Ω resistors and TDO 

should be left unconnected. 

All of the system bus signals have AGTL input, output, or input/output drivers. Except when servicing 
snoops, the system bus signals are tri-stated and pulled up by the termination resistors. Snoops are not 
permitted in the Deep Sleep state. 

The CMOS input signals are allowed to be in either the logic high or low state when the processor is in a 
low-power state. In the Auto Halt state these signals are allowed to toggle. These input buffers have no 
internal pull-up or pull-down resistors and system logic can use CMOS or Open-drain drivers to drive 
them.