Intel 1.70 GHz RH80532NC029256 Data Sheet
Product codes
RH80532NC029256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
23
section. PLL1 and PLL2 should be connected according to
Figure 2. Do not connect PLL2 directly to
V
SS
. Appendix A contains the RLC filter specification.
Figure 2. PLL RLC Filter
PLL1
PLL2
V
CCT
V0027-01
L1
C1
R1
3.2.3 Voltage
Identification
There are five voltage identification balls/pins on the Mobile Intel Celeron Processor. These signals can
be used to support automatic selection of V
be used to support automatic selection of V
CC
voltages. They are needed to cleanly support voltage
specification variations on current and future processors. VID[4:0] are defined in Table 7. The voltages
specified in the VID table are the Battery Optimized Mode V
specified in the VID table are the Battery Optimized Mode V
CC
voltages. The VID[4:0] signals are open
drain on the processor and need pull-up resistors to 3.3 V on the motherboard. Please refer to the mobile
VR guidelines provided by Intel for additional information.
VR guidelines provided by Intel for additional information.
Table 7. Mobile Intel Celeron Processor VID Values
VID[4:0] V
CC
(V) VID[4:0] V
CC
(V) VID[4:0] V
CC
(V) VID[4:0] V
CC
(V)
00000 1.750 01000 1.350 10000 0.975 11000 0.775
00001 1.700 01001 1.300 10001 0.950 11001 0.750
00010 1.650 01010 1.250 10010 0.925 11010 0.725
00011 1.600 01011 1.200 10011 0.900 11011 0.700
00100 1.550 01100 1.150 10100 0.875 11100 0.675
00101 1.500 01101 1.100 10101 0.850 11101 0.650
00110 1.450 01110 1.050 10110 0.825 11110 0.625
00111 1.400 01111 1.000 10111 0.800 11111 0.600
Figure 3 shows the system level connections for the VTTPWRGD signal. Please refer to the appropriate
VR and system level guidelines provided by Intel for more details.
VR and system level guidelines provided by Intel for more details.