Intel 1.70 GHz RH80532NC029256 Data Sheet
Product codes
RH80532NC029256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
83
7.
Processor Initialization and
Configuration
7.1 Description
The Mobile Intel Celeron Processor has some configuration options that are determined by hardware and
some that are determined by software. The processor samples its hardware configuration at reset on the
active-to-inactive transition of RESET#. The P6 Family of Processors Developer’s Manual describes
these configuration options. Some of the configuration options for the Mobile Intel Celeron Processor
are described in the remainder of this section.
some that are determined by software. The processor samples its hardware configuration at reset on the
active-to-inactive transition of RESET#. The P6 Family of Processors Developer’s Manual describes
these configuration options. Some of the configuration options for the Mobile Intel Celeron Processor
are described in the remainder of this section.
7.1.1
Quick Start Enable
Quick Start enabling is mandatory on the Mobile Intel Celeron Processor by strapping A15# low. When
the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled active on the
RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops from the bus
priority device but it does not support symmetric master snoops nor is the latching of interrupts
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick Start
state has been enabled.
the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled active on the
RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops from the bus
priority device but it does not support symmetric master snoops nor is the latching of interrupts
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick Start
state has been enabled.
7.1.2 System
Bus
Frequency
The current generation Mobile Intel Celeron Processor will only function with a system bus frequency of
133 MHz. The Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processors will support both
100-MHz and 133-MHz bus frequencies. Bit positions 18 to 19 of the Power-on Configuration register
indicates at which speed a processor will run.
133 MHz. The Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processors will support both
100-MHz and 133-MHz bus frequencies. Bit positions 18 to 19 of the Power-on Configuration register
indicates at which speed a processor will run.
7.1.3 APIC
Enable
The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to 1.5 V
and supplying an active PICCLK to the processor. Software can be used to disable the APIC if it is not
being used, after PICD[1:0] are sampled high when RESET# is deasserted and the processor has started
executing instructions.
and supplying an active PICCLK to the processor. Software can be used to disable the APIC if it is not
being used, after PICD[1:0] are sampled high when RESET# is deasserted and the processor has started
executing instructions.
7.2
Clock Frequencies and Ratios
The Mobile Intel Celeron Processor uses a clock design in which the bus clock is multiplied by a ratio to
produce the processor’s internal (or “core”) clock. The ratio used is programmed into the processor
during manufacturing. The bus ratio programmed into the processor is visible in bit positions 22 to 25
and 27 of the Power-on Configuration register. Table 28 shows the 5-bit codes in the Power-on
Configuration register and their corresponding bus ratios.
produce the processor’s internal (or “core”) clock. The ratio used is programmed into the processor
during manufacturing. The bus ratio programmed into the processor is visible in bit positions 22 to 25
and 27 of the Power-on Configuration register. Table 28 shows the 5-bit codes in the Power-on
Configuration register and their corresponding bus ratios.