Intel U1300 LE80538UE0042M Data Sheet
Product codes
LE80538UE0042M
Summary Tables of Changes
Specification Update
11
Stepping
Number
C0 D0
Dual
Core
Only
Plans ERRATA
AE1 X X
No
Fix
FST Instruction with Numeric and Null Segment Exceptions May
Take Numeric Exception with Incorrect FPU Operand Pointer
Take Numeric Exception with Incorrect FPU Operand Pointer
AE2 X X
No
Fix
Code Segment Limit Violation May Occur on 4-Gbyte Limit
Check
Check
AE3
Errata – Removed
AE4 X X
No
Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types May
Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
Crossing Page Boundaries with Inconsistent Memory Types May
Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
AE5 X X
No
Fix
Memory Aliasing with Inconsistent A and D Bits May Cause
Processor Deadlock
Processor Deadlock
AE6 X X
No
Fix
VM Bit Will Be Cleared on a Second Fault Handled by Task
Switch from Virtual-8086 (VM86)
Switch from Virtual-8086 (VM86)
AE7 X X
No
Fix
Page with PAT (Page Attribute Table) Set to USWC
(Uncacheable Speculative Write Combine) While Associated
MTRR (Memory Type Range Register) Is UC (Uncacheable) May
Consolidate to UC
(Uncacheable Speculative Write Combine) While Associated
MTRR (Memory Type Range Register) Is UC (Uncacheable) May
Consolidate to UC
AE8 X X
No
Fix
FPU Operand Pointer May Not Be Cleared following
FINIT/FNINIT
FINIT/FNINIT
AE9
X
X
No Fix
LTR Instruction May Result in Unexpected Behavior
AE10 X X
No
Fix
Invalid Entries in Page-Directory-Pointer-Table Register
(PDPTR) May Cause General Protection (#GP) Exception If the
Reserved Bits Are Set to One
(PDPTR) May Cause General Protection (#GP) Exception If the
Reserved Bits Are Set to One
AE11 X X
No
Fix
VMCALL When Executed during VMX Root Operation while CPL
> 0 May Not Generate #GP Fault
> 0 May Not Generate #GP Fault
AE12
X
X
No Fix
FP Inexact-result Exception Flag May Not Be Set
AE13 X X
No
Fix
A Locked Data Access That Spans across Two Pages
May Cause
the System to Hang
AE14
X
X
No Fix
MOV to/from Debug Registers Causes Debug Exception
AE15
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AE16 X X
No
Fix
Use of Memory Aliasing with Inconsistent Memory Type May
Cause a System Hang or a Machine Check Exception
Cause a System Hang or a Machine Check Exception
AE17 X X
No
Fix
Machine Check Exception May Occur When Interleaving Code
between Different Memory Types
between Different Memory Types
AE18 X
Fixed
Processor Digital Thermal Sensor (DTS) Readout Stops
Updating upon Returning from C3/C4 State
Updating upon Returning from C3/C4 State
AE19 X X
X No
Fix
Data Prefetch Performance Monitoring Event Can Only Be
Enabled on a Single Core
Enabled on a Single Core
AE20 X X
No
Fix
LOCK# Asserted during a Special Cycle Shutdown Transaction
May Unexpectedly Deassert
May Unexpectedly Deassert