Intel 4 2.26 GHz BX80532PE2260D User Manual
Product codes
BX80532PE2260D
22
Intel
®
Pentium
®
4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
2.7
Asynchronous GTL+ Signals
The Pentium 4 processor on 0.13 micron process does not use CMOS voltage levels on any signals
that connect to the processor. As a result, legacy input signals (such as A20M#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK#) use GTL+ input buffers.
that connect to the processor. As a result, legacy input signals (such as A20M#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK#) use GTL+ input buffers.
Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers.
PROCHOT# uses GTL+ input/output buffer. All of these signals follow the same DC requirements
as AGTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1
PROCHOT# uses GTL+ input/output buffer. All of these signals follow the same DC requirements
as AGTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1
transition) by the processor (the major difference between GTL+ and AGTL+). These signals do
not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the
Asynchronous GTL+ signals are required to be asserted for at least two BCLKs for the processor to
not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the
Asynchronous GTL+ signals are required to be asserted for at least two BCLKs for the processor to
recognize them. See
for the DC specifications for the Asynchronous GTL+ signal
groups. See
for additional timing requirements for entering and leaving the low power
states.
2.8
Test Access Port (TAP) Connection
Because of the voltage levels supported by other components in the Test Access Port (TAP) logic,
it is recommended that the Pentium 4 processor on 0.13 micron process be first in the TAP chain
it is recommended that the Pentium 4 processor on 0.13 micron process be first in the TAP chain
and followed by any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of accepting an input
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#.
connect to the rest of the chain unless one of the other components is capable of accepting an input
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#.
Two copies of each signal may be required, with each driving a different voltage level.
2.9
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock
(BCLK[1:0]).
(BCLK[1:0]).
defines the possible combinations of the signals, and the frequency
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency.
The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process currently operates at a
400 MHz, 533 MHz, or 800 MHz system bus frequency. The Pentium 4 processor Extreme Edition
supporting Hyper-Threading Technology currently operates at 800 MHz system bus frequency.
400 MHz, 533 MHz, or 800 MHz system bus frequency. The Pentium 4 processor Extreme Edition
supporting Hyper-Threading Technology currently operates at 800 MHz system bus frequency.
Individual processors will operate only at their specified system bus frequency.
and the appropriate platform design
guidelines.
Table 2-4. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
L
L
100 MHz
L
H
133 MHz
H
L
200 MHz
H
H
RESERVED