Intel ULV 383 LE80536VC0011M Data Sheet
Product codes
LE80536VC0011M
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
65
BNR# (I/O - GTL+)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
BP[3:2]# (I/O - GTL+)
The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are
outputs from the processor that indicate the status of breakpoints.
outputs from the processor that indicate the status of breakpoints.
BPM[1:0]# (I/O - GTL+)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
They are outputs from the processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
BPRI# (I - GTL+)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It
must be connected to the appropriate pins/balls on both agents on the system bus. Observing
BPRI# active (as asserted by the priority agent) causes the processor to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed and then releases the bus by deasserting BPRI#.
must be connected to the appropriate pins/balls on both agents on the system bus. Observing
BPRI# active (as asserted by the priority agent) causes the processor to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed and then releases the bus by deasserting BPRI#.
BREQ0# (I/O - GTL+)
The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates
that it wants ownership of the system bus by asserting the BREQ0# signal.
that it wants ownership of the system bus by asserting the BREQ0# signal.
During power-up configuration, the central agent must assert the BREQ0# bus signal. The
processor samples BREQ0# on the active-to-inactive transition of RESET#.
processor samples BREQ0# on the active-to-inactive transition of RESET#.
BSEL[1:0] (I - 3.3V Tolerant)
The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for
the system bus frequency. Table 35 shows the encoding scheme for BSEL[1:0]. The only
supported system bus frequency for the mobile Intel Celeron processor is 100 MHz. If another
frequency is used or if the BSEL[1:0] signals are not driven with “01” then the processor is not
guaranteed to function properly.
the system bus frequency. Table 35 shows the encoding scheme for BSEL[1:0]. The only
supported system bus frequency for the mobile Intel Celeron processor is 100 MHz. If another
frequency is used or if the BSEL[1:0] signals are not driven with “01” then the processor is not
guaranteed to function properly.