Intel D2500 DF8064101055400 Data Sheet

100

Datasheet - Volume 1 of 2

The following are the key features of Enhanced Intel SpeedStep Technology:

•

Applicable to Processor Core Voltage and Graphic Core Voltage (N2000 series only)

•

Multiple frequency and voltage points for optimal performance and power 

efficiency. These operating points are known as P-states.

•

Frequency selection is software controlled by writing to processor MSRs. The 

voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, VCC is ramped up 

in steps to an optimized voltage. This voltage is signaled by the VID pins to the 

voltage regulator. Once the voltage is established, the PLL locks on to the target 

frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

target frequency, then transitions to a lower voltage by signaling the target 

voltage on the VID pins.

•

The processor controls voltage ramp rates internally to ensure glitch-free 

transitions.

•

Because there is low transition latency between P-states, a significant number of 

transitions per second are possible.

•

Improved Thermal Monitor mode.
— When the on-die thermal sensor indicates that the die temperature is too high, 

the processor can automatically perform a transition to a lower frequency and 

voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up transition to the previous frequency and voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system level thermal management.

Dynamic Cache Sizing allows the processor to flush and disable a programmable 

number of L2 cache ways upon each Deeper Sleep entry under the following condition: 

•

The C0 timer that tracks continuous residency in the Normal state, has not expired. 

This timer is cleared during the first entry into Deeper Sleep to allow consecutive 

Deeper Sleep entries to shrink the L2 cache as needed.

•

The predefined L2 shrink threshold is triggered.

The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in 

the BBL_CR_CTL3 MSR. The C0 timer is referenced through the 

CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2 

cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the 

ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing 

decisions.