Intel D2500 DF8064101055400 Data Sheet
Product codes
DF8064101055400
Datasheet - Volume 1 of 2
99
7.1.6
Interface State Combinations
Table 7-56.G, S and C State combinations
Table 7-57.D, S and C state Combinations
7.2
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-
state have longer entry and exit latencies.
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-
state have longer entry and exit latencies.
Global
(G) State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System
Clocks
Description
G0
S0
C0
Full On
On
Full On
G0
S0
C1/C1E
Auto-Halt
On
Auto-Halt
G0
S0
C2/C2E
Stop-Grant
On
Stop-Grant
G0
S0
C4/C4E
Deeper Sleep
On
Deeper Sleep
G1
S3
Power off
Off except
RTC
Suspend to RAM
G1
S4
Power off
Off except
RTC
Suspend to Disk
G2
S5
Power off
Off except
RTC
Soft Off
G3
NA
Power Off
Power off
Hard Off
Graphics Adapter
(D) State
Sleep (S) State
(C) State
Description
D0
S0
C0
Full On, Displaying
D0
S0
C1
Auto-Halt, Displaying
D0
S0
C2/C4
Stop Grant/ Deeper Sleep,
Displaying
D3
S0
Any
Not Displaying
D3
S3
Not Displaying
Uncore host core power off.
Uncore host core power off.
D3
S4
Not Displaying
Suspend to disk
Uncore host core power off
Suspend to disk
Uncore host core power off