Intel 807 AV8062701079702 Data Sheet
Product codes
AV8062701079702
2.0
Interfaces
System Memory Interface
•
LPDDR3 down or DDR3L/DDR3L-RS Non-ECC Unbuffered Small Outline Dual In-
Line Memory Modules with a maximum of one DIMM per channel or down
•
LPDDR3 memory I/O Voltage of 1.2V. DDR3L/DDR3L-RS I/O Voltage of 1.35V
•
Two memory channels. Single-channel and dual-channel memory organization
modes
•
64-bit wide channels
•
Data burst length of eight for all memory organization modes
•
Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming 1600 MT/s
— 29.8 GB/s in dual-channel mode assuming 1866 MT/s
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming 1600 MT/s
— 29.8 GB/s in dual-channel mode assuming 1866 MT/s
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3L/DDR3L-RS and LPDDR3
protocols with two independent, 64-bit wide channels. It supports unbuffered non-ECC
memory per channel, allowing up to two device ranks per channel.
Table 3.
Processor DIMM Support Summary By Product
Processor Type
TDP (W)
Graphics
Configurat
ion
DIMM Per
Channel
Memory Speed
DDR3L /
DDR3L-RS
(MT/s)
LPDDR3
(MT/s)
Intel
®
Core
™
M Processor
6
GT2
1
1333, 1600
1333, 1600
Intel
®
Core
™
U-Processor
Line
28
GT3
1
1333, 1600
1600, 1866
Intel
®
Core
™
U-Processor
Line
15
GT3
1
1333, 1600
1600, 1866
Intel
®
Core
™
U-Processor
Line
15
GT2
1
1333, 1600
1333, 1600
Intel
®
Pentium
®
Processor
Intel
®
Celeron
®
Processor
15
GT1
1
1333, 1600
1333, 1600
2.1
2.1.1
Processor—Interfaces
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
March 2015
18
Order No.: 330834-004v1