Intel 807 AV8062701079702 Data Sheet
Product codes
AV8062701079702
Table 7.
DRAM System Memory Timing Support
Processor
DRAM
Device
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
tCWL
(tCK)
Command
Mode
Intel
®
Core
™
M
Processor
DDR3L/
DDR3L-RS
1333
8/9
8/9
8/9
7
1N/2N
1600
10/11
10/11
10/11
8
1N/2N
LPDDR3
1333
10
12
12
7
0.5N
1600
12
15
15
8
0.5N
Intel
®
Core
™
U-
Processor Line
Dual Core, GT3, 28W
Dual Core, GT3, 28W
TDP
Dual Core, GT3, 15W
Dual Core, GT3, 15W
TDP
DDR3L/
DDR3L-RS
1333
8/9
8/9
8/9
7
1N/2N
1600
10/11
10/11
10/11
8
1N/2N
LPDDR3
1600
12
15
15
8
0.5N
1866
14
17
17
11
0.5N
Intel
®
Core
™
U-
Processor Line
Dual Core, GT2, 15W
Dual Core, GT2, 15W
TDP
DDR3L/
DDR3L-RS
1333
8/9
8/9
8/9
7
1N/2N
1600
10/11
10/11
10/11
8
1N/2N
LPDDR3
1333
10
12
12
7
0.5N
1600
12
15
15
8
0.5N
Intel
®
Pentium
®
Processor
Intel
Intel
®
Celeron
®
Processor
DDR3L/
DDR3L-RS
1333
8/9
8/9
8/9
7
1N/2N
1600
10/11
10/11
10/11
8
1N/2N
LPDDR3
1333
10
12
12
7
0.5N
1600
12
15
15
8
0.5N
Note: tCL = CAS Latency, tRCD = Activate Command to READ or WRITE Command delay, tRP =
PRECHARGE Command Period, tCWL = CAS Write Latency, tCK = Clock Cycle
Intel
®
Fast Memory Access (Intel
®
FMA)
Just-in-Time Command Scheduling
The system memory controller has an advanced command scheduler where all
pending requests are examined simultaneously to determine the most efficient request
to be issued next. The most efficient request is picked from all pending requests and
issued to system memory Just-in-Time to make optimal use of Command Overlapping.
Thus, instead of having all memory access requests go individually through an
arbitration mechanism forcing requests to be executed one at a time, the requests can
be started without interfering with the current request, allowing for concurrent issuing
of requests. This allows for optimized bandwidth and reduced latency while
maintaining appropriate command spacing to meet system memory protocol.
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Pre-charge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.3
Processor—Interfaces
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
March 2015
20
Order No.: 330834-004v1