Intel 807 AV8062701079702 Data Sheet

CH B

CH A

B

B

C

B

B

C

CH A and CH B can be configured to be physical channels 0 or 1

B – The largest physical memory amount of the smaller size memory module

C – The remaining physical memory amount of the larger size memory module

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum

performance on real world applications. Addresses are ping-ponged between the

channels after each cache line (64-byte boundary). If there are two requests, and the

second request is to an address on the opposite channel from the first, that request

can be sent before data from the first request has returned. If two consecutive cache

lines are requested, both may be retrieved simultaneously, since they are ensured to

be on opposite channels. This mode is used when both Channel A and Channel B are

populated with the same amount of total memory.

The system memory controller incorporates a Data Scrambling feature to minimize the

impact of excessive di/dt on the platform system memory VRs due to successive 1s

and 0s on the data bus. Past experience has demonstrated that traffic on the data bus

is not random and can have energy concentrated at specific spectral harmonics

creating high di/dt, which is generally limited by data patterns that excite resonance

between the package inductance and on die capacitances. As a result, the system

memory controller uses a data scrambling feature to create pseudo-random patterns

on the system memory data bus to reduce the impact of any excessive di/dt.

The processor graphics contains a generation 8 graphics core architecture. This

enables substantial gains in performance and lower power consumption over previous

generations.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

22

Order No.: 330834-004v1