Intel 807 AV8062701079702 Data Sheet

While individual threads can request low-power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

The primary software interfaces for requesting low-power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions using I/O reads.

For legacy operating systems, P_LVLx I/O reads are converted within the processor to

the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result

in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be

enabled in the BIOS.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict

the range of I/O addresses that are trapped and emulate MWAIT like functionality.

Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx)

like request. The reads fall through like a normal I/O instruction.

When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The

MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx

I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a

wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.

The following are general rules for all core C-states, unless specified otherwise:
•

A core C-state is determined by the lowest numerical thread state (such as Thread

0 requests C1E state while Thread 1 requests C3 state, resulting in a core C1E

state). See the G, S, and C Interface State Combinations table.

•

A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered using an

MWAIT/Timed MWAIT instruction

— The deadline corresponding to the Timed MWAIT instruction expires

•

An interrupt directed toward a single thread wakes only that thread.

•

If any thread in a core is in active (in C0 state), the core's C-state will resolve to

C0 state.

•

Any interrupt coming into the processor package may wake any core.

•

A system reset re-initializes all processor cores.

The normal operating state of a core where code is being executed.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

48

Order No.: 330834-004v1