Intel 807 AV8062701079702 Data Sheet
Product codes
AV8062701079702
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All cores are in a power state deeper than C1/C1E state; however, the package
low-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
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All cores have requested C1 state using HLT or MWAIT(C1) and C1E auto-
promotion is enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E state.
Package C2 State
Package C2 state is an internal processor state that cannot be explicitly requested by
software. A processor enters Package C2 state when:
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All cores and graphics have requested a C3 or deeper power state; however,
constraints (LTR, programmed timer events in the near future, and so on) prevent
entry to any state deeper than C 2 state. Or,
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All cores and graphics are in the C3 or deeper power states, and a memory access
request is received. Upon completion of all outstanding memory requests, the
processor transitions back into a deeper package C-state.
Package C3 State
A processor enters the package C3 low-power state when:
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At least one core is in the C3 state.
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The other cores are in a C3 state or deeper power state and the processor has
been granted permission by the platform.
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The platform has not granted a request to a package C6/C7 or deeper state,
however, has allowed a package C6 state.
In package C3 state, the L3 shared cache is valid.
Package C6 State
A processor enters the package C6 low-power state when:
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At least one core is in the C6 state.
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The other cores are in a C6 or deeper power state and the processor has been
granted permission by the platform.
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The platform has not granted a package C7 state or deeper request; however, has
allowed a package C6 state.
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If the cores are requesting C7 state, but the platform is limiting to a package C6
state, the last level cache in this case can be flushed.
In package C6 state all cores have saved their architectural state and have had their
core voltages reduced to zero volts. It is possible the L3 shared cache is flushed and
turned off in package C6 state. If at least one core is requesting C6 state, the L3
cache will not be flushed.
Package C7 State
The processor enters the package C7 low-power state when all cores are in the C7
state. In package C7, the processor will take action to remove power from portions of
the system agent. The processor may enter a lower voltage package C7 state called
Package C7 Plus, operating at 1.3 V.
Processor—Power Management
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
March 2015
52
Order No.: 330834-004v1