Intel 807 AV8062701079702 Data Sheet

SM_RCOMP[2:0]

I

SM_PG_CNTL1

System Memory Power Gate Control: This signal

disables the platform memory VTT regulator in C8 and

deeper and S3 states.

CMOS OUTPUT

CFG[19:0]

Configuration Signals: The CFG signals have a default value of

'1' if not terminated on the board.
• CFG[2:0]: Reserved configuration lane. A test point may be

placed on the board for these lanes.

• CFG[3]: MSR Privacy Bit Feature

— 1 = Debug capability is determined by

IA32_Debug_Interface_MSR (C80h) bit[0] setting

— 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default

setting overridden

• CFG[4]: eDP enable

— 1 = Disabled
— 0 = Enabled

• CFG[19:5]: Reserved configuration lanes. A test point may

be placed on the board for these lands.

I/O

GTL

CFG_RCOMP

Configuration resistance compensation. Use a 49.9 Ω ±1%

resistor to ground.

—

FC_x

FC (Future Compatibility) signals are signals that are available for

compatibility with other processors. A test point may be placed

on the board for these lands.

—

IST_TRIGGER

Signal is for IFDIM testing only.

I

CMOS

IVR_ERROR

Signal is for debug. If both THERMTRIP# and this signal are

simultaneously asserted, the processor has encountered an

unrecoverable power delivery fault and has engaged automatic

shutdown as a result.

O

CMOS

RSVD
RSVD_TP

RESERVED: All signals that are RSVD must be left unconnected

on the board. Intel recommends that all RSVD_TP signals have

via test points.

No Connect

Test Point

TESTLO_x

TESTLO should be individually connected to V

SS

 through a

resistor.

—

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

74

Order No.: 330834-004v1