Intel 807 AV8062701079702 Data Sheet

This chapter describes the processor signals. The signals are arranged in functional

groups according to the associated interface or category. The following notations are

used to describe the signal type.

I

Input pin

O

Output pin

I/O

Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal

(see the following table).

CMOS

CMOS buffers. 1.05V- tolerant

Diff Clk

Differential clock

DDR3L/DDR3L-

RS

DDR3L/DDR3L-RS buffers: 1.35 V-tolerant

A

Analog reference or output. May be used as a threshold voltage or for buffer

compensation

GTL

Gunning Transceiver Logic signaling technology

Ref

Voltage reference signal

Asynchronous 

1

Signal has no timing relationship with any reference clock.

1. Qualifier for a buffer type.

SA_CK[0]/SA_CK#[0]

SB_CK[0]/SB_CK#[0]

Clocks: CK and its complement CK# signal make up a

differential clock pair. The crossing of the positive edge of CK

and the negative edge of its complement CK# are used to

sample the command and control signals.

O

SA_MA[15:0],

SB_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address.

O

SA_BS[2:0], SB_BS[2;0]

Bank Select: Signals used to define which bank a command

is being applied to.

O

SA_WE#, SB_WE#

Write Enable: These signals are used with RAS# and CAS#

to define the command being entered.

O

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

72

Order No.: 330834-004v1