Intel E5-1428L CM8062001144000 Data Sheet

Product codes
CM8062001144000
Page of 103
JTAG and TAP Signals
Table 29.
JTAG and TAP Signals
Signal Name
Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the
processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance. These are 100 MHz
signals.
PRDY_N
Probe Mode Ready is a processor output used by debug tools to determine
processor debug readiness.
PREQ_N
Probe Mode Request is used by debug tools to request debug operation of
the processor.
TCK
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TMS
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must
be driven low during power on Reset.
Serial VID Interface (SVID) Signals
Table 30.
SVID Signals
Signal Name
Description
SVIDALERT_N
Serial VID alert.
SVIDCLK
Serial VID clock.
SVIDDATA
Serial VID data out.
Processor Asynchronous Sideband and Miscellaneous
Signals
Table 31.
Processor Asynchronous Sideband Signals
Signal Name
Description
CATERR_N
Indicates that the system has experienced a fatal or catastrophic error and
cannot continue to operate. The processor will assert CATERR_N for
unrecoverable machine check errors and other internal unrecoverable
errors. It is expected that every processor in the system will wire-OR
CATERR_N for all processors. Since this is an I/O land, external agents are
allowed to assert this land which will cause the processor to take a machine
check exception. This signal is sampled after PWRGOOD assertion. On the
Intel
®
 Xeon
®
 processor v3 product families, CATERR_N is used for
signaling the following types of errors:
• Legacy MCERR's, CATERR_N is asserted for 16 BCLKs.
• Legacy IERR's, CATERR_N remains asserted until warm or cold reset.
ERROR_N[2:0]
Error status signals for integrated I/O (IIO) unit:
continued...   
4.7  
4.8  
4.9  
Intel
®
 Xeon
®
 Processor E5-1600 and E5-2600 v3 Product Families Signal Descriptions—Intel
®
Xeon
®
 Processor E5-1600 and E5-2600 v3 Product Families
Intel
®
 Xeon
®
 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical
September 2014
Datasheet
Order No.: 330783-001
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