Intel 9550 CM8063101049807 Data Sheet

27

1.

Measurement taken from single-ended waveform.

2.

The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; wn = 2 *fn. N_minUI = 12 

for Intel

®

 QuickPath Interconnect 4.8 Gt/s channel.

3.

Measurement taken from differential waveform.

4.

Measured from -150 mV to +150 mV on the differential waveform (derived from SYSCLK minus SYSCLK_N). The signal must 

be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the 

differential zero crossing. See 

5.

Measured at crossing point where the instantaneous voltage value of the rising edge SYSCLK equals the falling edge 

SYSCLK_N. See 

.

6.

Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all 

crossing points for this measurement. See 

.

7.

Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK_N. This is the maximum allowed 

variance in Vcross for any particular system. See 

.

8.

Defined as the maximum instantaneous voltage including overshoot. See 

9.

Defined as the minimum instantaneous voltage including undershoot. See 

.

10. T

Stable

 is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges 

before it is allowed to droop back into the VRB ±100 mV range. See 

.

T

Stable

Allowed time before ringback

500

ps

3, 10

T

REFCLK

-

JITTER

-

RMS

-

ONEPLL

Accumulated rms jitter over n UI of a 

given PLL model output in response to 

the jittery reference clock input. The 

PLL output is generated by convolving 

the measured reference clock phase 

jitter with a given PLL transfer 

function. Here n=12.

0.5

ps

2