Intel 9550 CM8063101049807 Data Sheet

29

33.33 MHz

66.66 MT/s (see note 1

)

1. This speed is the 1/4 SysClk Frequency.

2.40 GHz

4.8 GT/s

UI

avg

Average UI size at 4.8 GT/s

208.33

ps

N

MIN-UI-Validation

# of UI over which the eye mask voltage and 

timing spec needs to be validated

1E6

T

slew-rise-fall-pin

Defined as the slope of the rising or falling 

waveform as measured between ±100 mV of 

the differential transmitter output, data or 

clock

6

12

V/ns

V

Tx-diff-pp-pin

Transmitter differential swing

900

1300

mV

R

TX

Transmitter termination resistance

37.4

47.6

Ω

4

Z

TX_LINK_DETECT

Link Detection Resistor

500

2000

Ω

V

TX_LINK_DETECT

Link Detection Resistor Pull-up Voltage

max VCCIO

V

T

DATA_TERM_SKEW

Intel

®

 QPI

Skew between first to last data termination 

meeting Z

RX_LOW_CM_DC

600

UI

2

T

DATA_TERM_SKEW

Intel

®

 SMI

Skew between first to last data termination 

meeting Z

RX_LOW_CM_DC

780

UI

2

T

INBAND_RESET_SE

N

SE

Time taken by inband reset detector to sense 

Inband Reset

8k

256k

UI

T

CLK_DET

Time taken by clock detector to observe clock 

stability

8k

256k

UI

T

SYSCLK

-T

X

-V

ARIABILITY

Phase variability between reference Clk (at Tx 

input) and Tx output.

500

ps

TX

EQ-BOOST

Voltage ratio between the cursor and the 

post-cursor when transmitting successive 

ones

0

25

dB

3

V

T

X

-

CM

-

PIN

Transmitter data or clock common mode level 

23

27

%

V

T

X

-

CM

-

RIPPLE

-

PIN

Transmitter data or clock common mode 

ripple

0

14

%

8,9