Intel 9560 CM8063101049716 Data Sheet

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Offset 39h-3Bh provides maximum memory transfer rate on the Intel

® 

 Scalable 

Memory Interconnect (Intel

®

 SMI). Systems may need to read this offset to decide if 

processors and Intel

®

 75xx Scalable Memory Buffers support the same Intel

® 

 SMI 

transfer rate. Six 4-bit BCD digits are used to provide the maximum transfer rate in 
MT/s.

Example: A speed of 4.8 GT/s is shown as 004800h.

Offset 3Ch-3Eh provides minimum “operating” memory transfer rate on the Intel

® 

 

Scalable Memory Interconnect. Six 4-bit BCD digits are used to provide the minimum 
transfer rate in MT/s. 

Offset 3Fh-40h is the nominal processor Uncore voltage for this part, rounded to the 
next thousandthin mV and reflected in BCD.

Example: 1200 mV is stored as 3Fh: 00h, 40h: 12h.

Offset 41h and 42h contain the Uncore voltage tolerances, high and low respectively. 
These use a decimal to Hexadecimal conversion. Example: 20 mV tolerance would be 
saved as 14h.

This section contains cache related data.

Offset 46h-47h is the L3 cache size field. The field reflects the size of the level three 
cache in MBytes in bcd format.

Example: The Intel

®

 Itanium

®

 Processor 9300 Series has a 24 MB L3 cache. Thus, 

offsets 46h & 47h will contain 24 & 00 respectively.

Offset 48h-49h is the nominal processor cache voltage for the Intel

®

 Itanium

®

 

Processor 9300 Series processor, rounded to the next thousandth, in mV and is 
reflected in bcd. 

These fields are RESERVED for the Intel

®

 Itanium

®

 Processor 9500 Series.

Offset 4Ah and 4Bh contain the cache voltage tolerances, high and low respectively. 
These use a decimal to Hexadecimal conversion. 

Example: 20 mV tolerance would be saved as 14h. 

These fields are RESERVED for the Intel

®

 Itanium

®

 Processor 9500 Series.