Intel 9560 CM8063101049716 Data Sheet

156

The de-assertion threshold is expressed as the number of degrees C below the 
thermalert hot threshold value in Hex format.

Example: reading offset 6Bh=00001010 and 6Ch=0000010, then programming the 
CSRs with these values means THERMALERT_N will be asserted when junction 
temperature rises to 10C below the PROCHOT_N (thermal throttle) threshold and will 
remain asserted until the junction temperature drops to 12°C below the PROCHOT_N 
threshold.

Offset 6Dh is programmed with 2 Hex digits representing the max TDP of the part.

Example: 6Dh = 0xB9 indicates a 185 W part.

Offset 6Eh contains the recommended TControl spec in degrees C below PROCHOT_N 
temperature in Hex format.

This section provides information on key features that the platform may need to 
understand without powering on the processor.

For the Intel

®

 Itanium

®

 Processor 9300 Series, offset 72h-75h contains a copy of 

results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide 
instruction and feature support by product family. These fields are RESERVED for the 
Intel

®

 Itanium

®

 Processor 9500 Series processor.

Offset 78h-79h provides additional feature information from the processor. This field is 
defined as follows:

At offset 7Bh, a 4-bit Hex digit is used to tell how many devices are in the TAP Chain. 
The four bits are the most significant bits at this offset.

Since Intel

®

 Itanium

®

 Processor 9300 Series and Intel

®

 Itanium

®

 Processor 9500 

Series processors have one TAP per core plus a sysint TAP, this field would be set to 50h 
for the Intel

®

 Itanium

®

 Processor 9300 Series processor and 90 for the Intel

®

 

4-32

Reserved

3

Thermal calibration offset byte present

2

Scratch (OEM) EEPROM present (set if there is a scratch ROM at offset 80 - FFh)

1

Core VID present (set if there is a VID provided by the processor)

0

Reserved