Intel Core 2 Extreme QX9300 BX80562QX9300 User Manual
Product codes
BX80562QX9300
Low Power Features
12
Datasheet
Figure 1.
Core Low Power States
Stop
Grant
C1/MWAIT
C0
C1/Auto
Halt
Halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
+ __ STPCLK# assertion and de-assertion have no effect if a core is in C2, C3 or C4.
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
deasserte
STPCLK#
deasserted
STPCLK#
asserted
Core State
Break
MWAIT(C1)
HLT instruction
Halt break
Core State
Break
P_LVL2 or
MWAIT(C2)
Core State
Break
P_LVL4 or
MWAIT(C4) Core State
Break
P_LVL3 or
MWAIT(C3)
C4
+
C3
+
C2
+