Intel Core 2 Extreme QX9300 BX80562QX9300 User Manual

58

Datasheet

BPM_2[1]#

BPM_2[0;3:2]
#

Output

Input/

Output

BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and 
performance monitor signals of the second die. They are outputs 
from the processor that indicate the status of breakpoints and 
programmable counters used for monitoring processor 
performance. BPM_2[3:0]# should connect the appropriate pins of 
all processor FSB agents.This includes debug or performance 
monitoring tools.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of 
the FSB. It must connect the appropriate pins of both FSB agents. 
Observing BPRI# active (as asserted by the priority agent) causes 
the other agent to stop issuing new requests, unless such requests 
are part of an ongoing locked operation. The priority agent keeps 
BPRI# asserted until all of its requests are completed, then 
releases the bus by deasserting BPRI#.

BR0#

Input/

Output

BR0# is used by the processor to request the bus. The arbitration 
is done between the processor (Symmetric Agent) and GMCH (High 
Priority Agent). 

BR1#

Input/

Output

Arbitration Request signal for the second die.
BR1# is connected to the first die within the package, allowing two 
dies within quad-core parts to artitrite for the bus. This pin is 
fundamentally provided for debug capabilities and should be left as 
NC.

BSEL[2:0]

Output

BSEL[2:0] (Bus Select) are used to select the processor input clock 
frequency. 

 defines the possible combinations of the signals 

and the frequency associated with each combination. The required 
frequency is determined by the processor, chipset and clock 
synthesizer. All agents must operate at the same frequency. 

COMP[3:0]

Analog

COMP[3:0] must be terminated on the system board using 
precision (1% tolerance) resistors.